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authorLinus Torvalds <torvalds@linux-foundation.org>2014-03-31 15:27:37 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2014-03-31 15:27:37 -0700
commit01d5f3b598b18a5035426c30801adf65822dbd0c (patch)
tree156c85882676ff9fb1759505ef9eee89814c8629 /arch
parent9d919e8d5b04e987b0378cfd73df6cdd2b19e9db (diff)
parent03803ef66d22702af124d21552f90ac32da9fef5 (diff)
Merge branch 'for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata
Pull libata updates from Tejun Heo: "A lot of activities on libata side this time. - A lot of changes around ahci. Various embedded platforms are implementing ahci controllers. Some were built atop ahci_platform, others were doing their own things. Hans made some structural changes to libahci and librarized ahci_platform so that ahci platform drivers can share more common code. A couple platform drivers are added on top of that and several are added to replace older drivers which were doing their own things (older ones are scheduled to be removed). - Dan finishes the patchset to make libata PM operations asynchronous. Combined with one patch being routed through scsi, this should speed resume measurably. - Various fixes and cleanups from Bartlomiej and others" * 'for-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata: (61 commits) ata: fix Marvell SATA driver dependencies ata: fix ARASAN CompactFlash PATA driver dependencies ata: remove superfluous casts ata: sata_highbank: remove superfluous cast ata: fix Calxeda Highbank SATA driver dependencies ata: fix R-Car SATA driver dependencies ARM: davinci: da850: update SATA AHCI support ata: add new-style AHCI platform driver for DaVinci DA850 AHCI controller ata: move library code from ahci_platform.c to libahci_platform.c ata: ahci_platform: fix ahci_platform_data->suspend method handling libata: remove unused ata_sas_port_async_resume() stub libata.h: add stub for ata_sas_port_resume libata: async resume libata, libsas: kill pm_result and related cleanup ata: Fix compiler warning with APM X-Gene host controller driver arm64: Add APM X-Gene SoC AHCI SATA host controller DTS entries ata: Add APM X-Gene SoC AHCI SATA host controller driver Documentation: Add documentation for the APM X-Gene SoC SATA host controller DTS binding arm64: Add APM X-Gene SoC 15Gbps Multi-purpose PHY DTS entries ata: ahci_sunxi: fix code formatting ...
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-davinci/da850.c2
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c99
-rw-r--r--arch/arm64/boot/dts/apm-storm.dtsi152
3 files changed, 161 insertions, 92 deletions
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 2ab00434b2eb..85399c98f84a 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -472,7 +472,7 @@ static struct clk_lookup da850_clks[] = {
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
CLK("vpif", NULL, &vpif_clk),
- CLK("ahci", NULL, &sata_clk),
+ CLK("ahci_da850", NULL, &sata_clk),
CLK("davinci-rproc.0", NULL, &dsp_clk),
CLK("ehrpwm", "fck", &ehrpwm_clk),
CLK("ehrpwm", "tbclk", &ehrpwm_tbclk),
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 0486cdf28c8d..56ea41d5f849 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -1020,7 +1020,6 @@ int __init da8xx_register_spi_bus(int instance, unsigned num_chipselect)
}
#ifdef CONFIG_ARCH_DAVINCI_DA850
-
static struct resource da850_sata_resources[] = {
{
.start = DA850_SATA_BASE,
@@ -1028,103 +1027,22 @@ static struct resource da850_sata_resources[] = {
.flags = IORESOURCE_MEM,
},
{
+ .start = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG,
+ .end = DA8XX_SYSCFG1_BASE + DA8XX_PWRDN_REG + 0x3,
+ .flags = IORESOURCE_MEM,
+ },
+ {
.start = IRQ_DA850_SATAINT,
.flags = IORESOURCE_IRQ,
},
};
-/* SATA PHY Control Register offset from AHCI base */
-#define SATA_P0PHYCR_REG 0x178
-
-#define SATA_PHY_MPY(x) ((x) << 0)
-#define SATA_PHY_LOS(x) ((x) << 6)
-#define SATA_PHY_RXCDR(x) ((x) << 10)
-#define SATA_PHY_RXEQ(x) ((x) << 13)
-#define SATA_PHY_TXSWING(x) ((x) << 19)
-#define SATA_PHY_ENPLL(x) ((x) << 31)
-
-static struct clk *da850_sata_clk;
-static unsigned long da850_sata_refclkpn;
-
-/* Supported DA850 SATA crystal frequencies */
-#define KHZ_TO_HZ(freq) ((freq) * 1000)
-static unsigned long da850_sata_xtal[] = {
- KHZ_TO_HZ(300000),
- KHZ_TO_HZ(250000),
- 0, /* Reserved */
- KHZ_TO_HZ(187500),
- KHZ_TO_HZ(150000),
- KHZ_TO_HZ(125000),
- KHZ_TO_HZ(120000),
- KHZ_TO_HZ(100000),
- KHZ_TO_HZ(75000),
- KHZ_TO_HZ(60000),
-};
-
-static int da850_sata_init(struct device *dev, void __iomem *addr)
-{
- int i, ret;
- unsigned int val;
-
- da850_sata_clk = clk_get(dev, NULL);
- if (IS_ERR(da850_sata_clk))
- return PTR_ERR(da850_sata_clk);
-
- ret = clk_prepare_enable(da850_sata_clk);
- if (ret)
- goto err0;
-
- /* Enable SATA clock receiver */
- val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
- val &= ~BIT(0);
- __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
-
- /* Get the multiplier needed for 1.5GHz PLL output */
- for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
- if (da850_sata_xtal[i] == da850_sata_refclkpn)
- break;
-
- if (i == ARRAY_SIZE(da850_sata_xtal)) {
- ret = -EINVAL;
- goto err1;
- }
-
- val = SATA_PHY_MPY(i + 1) |
- SATA_PHY_LOS(1) |
- SATA_PHY_RXCDR(4) |
- SATA_PHY_RXEQ(1) |
- SATA_PHY_TXSWING(3) |
- SATA_PHY_ENPLL(1);
-
- __raw_writel(val, addr + SATA_P0PHYCR_REG);
-
- return 0;
-
-err1:
- clk_disable_unprepare(da850_sata_clk);
-err0:
- clk_put(da850_sata_clk);
- return ret;
-}
-
-static void da850_sata_exit(struct device *dev)
-{
- clk_disable_unprepare(da850_sata_clk);
- clk_put(da850_sata_clk);
-}
-
-static struct ahci_platform_data da850_sata_pdata = {
- .init = da850_sata_init,
- .exit = da850_sata_exit,
-};
-
static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
static struct platform_device da850_sata_device = {
- .name = "ahci",
+ .name = "ahci_da850",
.id = -1,
.dev = {
- .platform_data = &da850_sata_pdata,
.dma_mask = &da850_sata_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
@@ -1134,9 +1052,8 @@ static struct platform_device da850_sata_device = {
int __init da850_register_sata(unsigned long refclkpn)
{
- da850_sata_refclkpn = refclkpn;
- if (!da850_sata_refclkpn)
- return -EINVAL;
+ /* please see comment in drivers/ata/ahci_da850.c */
+ BUG_ON(refclkpn != 100 * 1000 * 1000);
return platform_device_register(&da850_sata_device);
}
diff --git a/arch/arm64/boot/dts/apm-storm.dtsi b/arch/arm64/boot/dts/apm-storm.dtsi
index d37d7369e260..93f4b2dd9248 100644
--- a/arch/arm64/boot/dts/apm-storm.dtsi
+++ b/arch/arm64/boot/dts/apm-storm.dtsi
@@ -176,6 +176,87 @@
reg-names = "csr-reg";
clock-output-names = "eth8clk";
};
+
+ sataphy1clk: sataphy1clk@1f21c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f21c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sataphy1clk";
+ status = "disabled";
+ csr-offset = <0x4>;
+ csr-mask = <0x00>;
+ enable-offset = <0x0>;
+ enable-mask = <0x06>;
+ };
+
+ sataphy2clk: sataphy1clk@1f22c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f22c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sataphy2clk";
+ status = "ok";
+ csr-offset = <0x4>;
+ csr-mask = <0x3a>;
+ enable-offset = <0x0>;
+ enable-mask = <0x06>;
+ };
+
+ sataphy3clk: sataphy1clk@1f23c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f23c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sataphy3clk";
+ status = "ok";
+ csr-offset = <0x4>;
+ csr-mask = <0x3a>;
+ enable-offset = <0x0>;
+ enable-mask = <0x06>;
+ };
+
+ sata01clk: sata01clk@1f21c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f21c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sata01clk";
+ csr-offset = <0x4>;
+ csr-mask = <0x05>;
+ enable-offset = <0x0>;
+ enable-mask = <0x39>;
+ };
+
+ sata23clk: sata23clk@1f22c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f22c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sata23clk";
+ csr-offset = <0x4>;
+ csr-mask = <0x05>;
+ enable-offset = <0x0>;
+ enable-mask = <0x39>;
+ };
+
+ sata45clk: sata45clk@1f23c000 {
+ compatible = "apm,xgene-device-clock";
+ #clock-cells = <1>;
+ clocks = <&socplldiv2 0>;
+ reg = <0x0 0x1f23c000 0x0 0x1000>;
+ reg-names = "csr-reg";
+ clock-output-names = "sata45clk";
+ csr-offset = <0x4>;
+ csr-mask = <0x05>;
+ enable-offset = <0x0>;
+ enable-mask = <0x39>;
+ };
};
serial0: serial@1c020000 {
@@ -187,5 +268,76 @@
interrupt-parent = <&gic>;
interrupts = <0x0 0x4c 0x4>;
};
+
+ phy1: phy@1f21a000 {
+ compatible = "apm,xgene-phy";
+ reg = <0x0 0x1f21a000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&sataphy1clk 0>;
+ status = "disabled";
+ apm,tx-boost-gain = <30 30 30 30 30 30>;
+ apm,tx-eye-tuning = <2 10 10 2 10 10>;
+ };
+
+ phy2: phy@1f22a000 {
+ compatible = "apm,xgene-phy";
+ reg = <0x0 0x1f22a000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&sataphy2clk 0>;
+ status = "ok";
+ apm,tx-boost-gain = <30 30 30 30 30 30>;
+ apm,tx-eye-tuning = <1 10 10 2 10 10>;
+ };
+
+ phy3: phy@1f23a000 {
+ compatible = "apm,xgene-phy";
+ reg = <0x0 0x1f23a000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&sataphy3clk 0>;
+ status = "ok";
+ apm,tx-boost-gain = <31 31 31 31 31 31>;
+ apm,tx-eye-tuning = <2 10 10 2 10 10>;
+ };
+
+ sata1: sata@1a000000 {
+ compatible = "apm,xgene-ahci";
+ reg = <0x0 0x1a000000 0x0 0x1000>,
+ <0x0 0x1f210000 0x0 0x1000>,
+ <0x0 0x1f21d000 0x0 0x1000>,
+ <0x0 0x1f21e000 0x0 0x1000>,
+ <0x0 0x1f217000 0x0 0x1000>;
+ interrupts = <0x0 0x86 0x4>;
+ status = "disabled";
+ clocks = <&sata01clk 0>;
+ phys = <&phy1 0>;
+ phy-names = "sata-phy";
+ };
+
+ sata2: sata@1a400000 {
+ compatible = "apm,xgene-ahci";
+ reg = <0x0 0x1a400000 0x0 0x1000>,
+ <0x0 0x1f220000 0x0 0x1000>,
+ <0x0 0x1f22d000 0x0 0x1000>,
+ <0x0 0x1f22e000 0x0 0x1000>,
+ <0x0 0x1f227000 0x0 0x1000>;
+ interrupts = <0x0 0x87 0x4>;
+ status = "ok";
+ clocks = <&sata23clk 0>;
+ phys = <&phy2 0>;
+ phy-names = "sata-phy";
+ };
+
+ sata3: sata@1a800000 {
+ compatible = "apm,xgene-ahci";
+ reg = <0x0 0x1a800000 0x0 0x1000>,
+ <0x0 0x1f230000 0x0 0x1000>,
+ <0x0 0x1f23d000 0x0 0x1000>,
+ <0x0 0x1f23e000 0x0 0x1000>;
+ interrupts = <0x0 0x88 0x4>;
+ status = "ok";
+ clocks = <&sata45clk 0>;
+ phys = <&phy3 0>;
+ phy-names = "sata-phy";
+ };
};
};