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authorTirupathi Reddy <tirupath@codeaurora.org>2017-01-02 09:33:07 +0530
committerTirupathi Reddy <tirupath@codeaurora.org>2017-01-05 05:25:27 +0530
commit065bd0b8a0e2f48ee18498bcbe77f980947a77ae (patch)
tree57be7b2e76091efba2888eade385f28d51312ca9 /arch
parent8bb66a7e413624884e697d295b7e136f96209cd9 (diff)
ARM: dts: msm: Add APC0/1 CPR instances for sdm660
Add CPR device nodes with required configuration for supporting closed-loop operation for APC0/1 CPR instances in sdm660. CRs-Fixed: 1105923 Change-Id: I6c085f7fb3a491b595f27c959468589b741cd2c0 Signed-off-by: Tirupathi Reddy <tirupath@codeaurora.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/boot/dts/qcom/sdm660-regulator.dtsi157
-rw-r--r--arch/arm/boot/dts/qcom/sdm660.dtsi38
2 files changed, 175 insertions, 20 deletions
diff --git a/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi
index fc88c324e5e2..479a9fdd91ca 100644
--- a/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-regulator.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -10,6 +10,7 @@
* GNU General Public License for more details.
*/
+#include <dt-bindings/clock/qcom,gcc-sdm660.h>
#include <dt-bindings/clock/qcom,gpu-sdm660.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -633,4 +634,158 @@
};
};
};
+
+ /* APC0 CPR Controller node for Silver cluster */
+ apc0_cpr: cprh-ctrl@179c8000 {
+ compatible = "qcom,cprh-sdm660-kbss-regulator";
+ reg = <0x179c8000 0x4000>, <0x00784000 0x1000>;
+ reg-names = "cpr_ctrl", "fuse_base";
+ clocks = <&clock_gcc GCC_HMSS_RBCPR_CLK>;
+ clock-names = "core_clk";
+ qcom,cpr-ctrl-name = "apc0";
+ qcom,cpr-controller-id = <0>;
+
+ qcom,cpr-sensor-time = <1000>;
+ qcom,cpr-loop-time = <5000000>;
+ qcom,cpr-idle-cycles = <15>;
+ qcom,cpr-up-down-delay-time = <3000>;
+ qcom,cpr-step-quot-init-min = <12>;
+ qcom,cpr-step-quot-init-max = <14>;
+ qcom,cpr-count-mode = <0>; /* All at once */
+ qcom,cpr-count-repeat = <14>;
+ qcom,cpr-down-error-step-limit = <1>;
+ qcom,cpr-up-error-step-limit = <1>;
+ qcom,cpr-corner-switch-delay-time = <1042>;
+ qcom,cpr-voltage-settling-time = <1760>;
+
+ qcom,apm-threshold-voltage = <872000>;
+ qcom,apm-crossover-voltage = <872000>;
+ qcom,apm-hysteresis-voltage = <20000>;
+ qcom,voltage-step = <4000>;
+ qcom,voltage-base = <400000>;
+ qcom,cpr-saw-use-unit-mV;
+
+ qcom,cpr-panic-reg-addr-list =
+ <0x179cbaa4 0x17912c18>;
+ qcom,cpr-panic-reg-name-list =
+ "PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS";
+
+ thread@0 {
+ qcom,cpr-thread-id = <0>;
+ qcom,cpr-consecutive-up = <0>;
+ qcom,cpr-consecutive-down = <2>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <2>;
+
+ apc0_pwrcl_vreg: regulator {
+ regulator-name = "apc0_pwrcl_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <8>;
+
+ qcom,cpr-fuse-corners = <5>;
+ qcom,cpr-fuse-combos = <16>;
+ qcom,cpr-speed-bins = <2>;
+ qcom,cpr-speed-bin-corners = <8 8>;
+ qcom,cpr-corners = <8>;
+ qcom,cpr-corner-fmax-map = <2 3 4 5 8>;
+
+ qcom,cpr-voltage-ceiling =
+ <724000 724000 724000 788000 868000
+ 924000 988000 1068000>;
+
+ qcom,cpr-voltage-floor =
+ <588000 588000 596000 652000 712000
+ 744000 784000 844000>;
+
+ qcom,corner-frequencies =
+ <300000000 633600000 902400000
+ 1113600000 1401600000 1536000000
+ 1747200000 1843200000>;
+
+ qcom,allow-voltage-interpolation;
+ qcom,allow-quotient-interpolation;
+ qcom,cpr-scaled-open-loop-voltage-as-ceiling;
+ };
+ };
+ };
+
+ /* APC1 CPR Controller node for Gold cluster */
+ apc1_cpr: cprh-ctrl@179c4000 {
+ compatible = "qcom,cprh-sdm660-kbss-regulator";
+ reg = <0x179c4000 0x4000>, <0x00784000 0x1000>;
+ reg-names = "cpr_ctrl", "fuse_base";
+ clocks = <&clock_gcc GCC_HMSS_RBCPR_CLK>;
+ clock-names = "core_clk";
+ qcom,cpr-ctrl-name = "apc1";
+ qcom,cpr-controller-id = <1>;
+
+ qcom,cpr-sensor-time = <1000>;
+ qcom,cpr-loop-time = <5000000>;
+ qcom,cpr-idle-cycles = <15>;
+ qcom,cpr-up-down-delay-time = <3000>;
+ qcom,cpr-step-quot-init-min = <12>;
+ qcom,cpr-step-quot-init-max = <14>;
+ qcom,cpr-count-mode = <0>; /* All at once */
+ qcom,cpr-count-repeat = <14>;
+ qcom,cpr-down-error-step-limit = <1>;
+ qcom,cpr-up-error-step-limit = <1>;
+ qcom,cpr-corner-switch-delay-time = <1042>;
+ qcom,cpr-voltage-settling-time = <1760>;
+
+ qcom,apm-threshold-voltage = <872000>;
+ qcom,apm-crossover-voltage = <872000>;
+ qcom,apm-hysteresis-voltage = <20000>;
+ qcom,voltage-step = <4000>;
+ qcom,voltage-base = <400000>;
+ qcom,cpr-saw-use-unit-mV;
+
+ qcom,cpr-panic-reg-addr-list =
+ <0x179c7aa4 0x17812c18>;
+ qcom,cpr-panic-reg-name-list =
+ "PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS";
+
+ thread@0 {
+ qcom,cpr-thread-id = <0>;
+ qcom,cpr-consecutive-up = <0>;
+ qcom,cpr-consecutive-down = <2>;
+ qcom,cpr-up-threshold = <2>;
+ qcom,cpr-down-threshold = <2>;
+
+ apc1_perfcl_vreg: regulator {
+ regulator-name = "apc1_perfcl_corner";
+ regulator-min-microvolt = <1>;
+ regulator-max-microvolt = <7>;
+
+ qcom,cpr-fuse-corners = <5>;
+ qcom,cpr-fuse-combos = <16>;
+ qcom,cpr-speed-bins = <2>;
+ qcom,cpr-speed-bin-corners = <7 7>;
+ qcom,cpr-corners = <7>;
+ qcom,cpr-corner-fmax-map = <2 3 4 6 7>;
+
+ qcom,cpr-voltage-ceiling =
+ <724000 724000 788000 868000
+ 924000 988000 1068000>;
+
+ qcom,cpr-voltage-floor =
+ <588000 596000 652000 712000
+ 744000 784000 844000>;
+
+ qcom,corner-frequencies =
+ /* Speed bin 0 */
+ <300000000 1113600000 1401600000
+ 1747200000 1958400000 2150400000
+ 2457600000>,
+
+ /* Speed bin 1 */
+ <300000000 1113600000 1401600000
+ 1747200000 1958400000 2150400000
+ 2208000000>;
+
+ qcom,allow-voltage-interpolation;
+ qcom,allow-quotient-interpolation;
+ qcom,cpr-scaled-open-loop-voltage-as-ceiling;
+ };
+ };
+ };
};
diff --git a/arch/arm/boot/dts/qcom/sdm660.dtsi b/arch/arm/boot/dts/qcom/sdm660.dtsi
index a12a43ffa64c..20385d850527 100644
--- a/arch/arm/boot/dts/qcom/sdm660.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660.dtsi
@@ -1102,31 +1102,31 @@
qcom,pwrcl-speedbin0-v0 =
< 300000000 0x0004000f 0x01200020 0x1 1 >,
- < 633600000 0x05040021 0x03200020 0x1 1 >,
- < 902400000 0x0404002f 0x04260026 0x1 2 >,
- < 1113600000 0x0404003a 0x052e002e 0x2 3 >,
- < 1401600000 0x04040049 0x073a003a 0x2 4 >,
- < 1536000000 0x04040050 0x08400040 0x3 5 >,
- < 1747200000 0x0404005b 0x09480048 0x3 6 >,
- < 1843200000 0x04040060 0x094c004c 0x3 7 >;
+ < 633600000 0x05040021 0x03200020 0x1 2 >,
+ < 902400000 0x0404002f 0x04260026 0x1 3 >,
+ < 1113600000 0x0404003a 0x052e002e 0x2 4 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 5 >,
+ < 1536000000 0x04040050 0x08400040 0x3 6 >,
+ < 1747200000 0x0404005b 0x09480048 0x3 7 >,
+ < 1843200000 0x04040060 0x094c004c 0x3 8 >;
qcom,perfcl-speedbin0-v0 =
< 300000000 0x0004000f 0x01200020 0x1 1 >,
- < 1113600000 0x0404003a 0x052e002e 0x1 1 >,
- < 1401600000 0x04040049 0x073a003a 0x2 2 >,
- < 1747200000 0x0404005b 0x09480048 0x2 3 >,
- < 1958400000 0x04040066 0x0a510051 0x3 4 >,
- < 2150400000 0x04040070 0x0b590059 0x3 5 >,
- < 2457600000 0x04040080 0x0c660066 0x3 6 >;
+ < 1113600000 0x0404003a 0x052e002e 0x1 2 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 3 >,
+ < 1747200000 0x0404005b 0x09480048 0x2 4 >,
+ < 1958400000 0x04040066 0x0a510051 0x3 5 >,
+ < 2150400000 0x04040070 0x0b590059 0x3 6 >,
+ < 2457600000 0x04040080 0x0c660066 0x3 7 >;
qcom,perfcl-speedbin1-v0 =
< 300000000 0x0004000f 0x01200020 0x1 1 >,
- < 1113600000 0x0404003a 0x052e002e 0x1 1 >,
- < 1401600000 0x04040049 0x073a003a 0x2 2 >,
- < 1747200000 0x0404005b 0x09480048 0x2 3 >,
- < 1958400000 0x04040066 0x0a510051 0x3 4 >,
- < 2150400000 0x04040070 0x0b590059 0x3 5 >,
- < 2208000000 0x04040073 0x0b5c005c 0x3 6 >;
+ < 1113600000 0x0404003a 0x052e002e 0x1 2 >,
+ < 1401600000 0x04040049 0x073a003a 0x2 3 >,
+ < 1747200000 0x0404005b 0x09480048 0x2 4 >,
+ < 1958400000 0x04040066 0x0a510051 0x3 5 >,
+ < 2150400000 0x04040070 0x0b590059 0x3 6 >,
+ < 2208000000 0x04040073 0x0b5c005c 0x3 7 >;
qcom,up-timer = <1000 1000>;
qcom,down-timer = <1000 1000>;