Merge "ARM: dts: msm: Add support for GDSCs for MSMfalcon"

1 files changed, 98 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
index 11700b5b69ba..7c4e7f0ee55a 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
@@ -544,3 +544,101 @@
 
 #include "msmfalcon-ion.dtsi"
 #include "msmfalcon-regulator.dtsi"
+#include "msm-gdsc-cobalt.dtsi"
+
+&gdsc_usb30 {
+	clock-names = "core_clk";
+	clocks = <&clock_gcc GCC_USB30_MASTER_CLK>;
+	status = "ok";
+};
+
+&gdsc_ufs {
+	clock-names = "bus_clk", "ice_clk", "unipro_clk";
+	clocks = <&clock_gcc GCC_UFS_AXI_CLK>,
+		 <&clock_gcc GCC_UFS_ICE_CORE_CLK>,
+		 <&clock_gcc GCC_UFS_UNIPRO_CORE_CLK>;
+	status = "ok";
+};
+
+&gdsc_bimc_smmu {
+	clock-names = "bus_clk";
+	clocks = <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
+	proxy-supply = <&gdsc_bimc_smmu>;
+	qcom,proxy-consumer-enable;
+	status = "ok";
+};
+
+&gdsc_hlos1_vote_lpass_adsp {
+	status = "ok";
+};
+
+&gdsc_hlos1_vote_lpass_core {
+	status = "ok";
+};
+
+&gdsc_venus {
+	clock-names = "bus_clk", "core_clk";
+	clocks = <&clock_mmss MMSS_VIDEO_AXI_CLK>,
+		 <&clock_mmss MMSS_VIDEO_CORE_CLK>;
+	status = "ok";
+};
+
+&gdsc_venus_core0 {
+	clock-names = "core0_clk";
+	clocks = <&clock_mmss MMSS_VIDEO_SUBCORE0_CLK>;
+	qcom,support-hw-trigger;
+	status = "ok";
+};
+
+&gdsc_camss_top {
+	clock-names = "bus_clk", "vfe_axi";
+	clocks = <&clock_mmss MMSS_CAMSS_CPP_AXI_CLK>,
+		 <&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>;
+	status = "ok";
+};
+
+&gdsc_vfe0 {
+	clock-names = "core0_clk" , "core0_stream_clk";
+	clocks = <&clock_mmss MMSS_CAMSS_VFE0_CLK>,
+		 <&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>;
+	parent-supply = <&gdsc_camss_top>;
+	status = "ok";
+};
+
+&gdsc_vfe1 {
+	clock-names = "core1_clk" , "core1_stream_clk";
+	clocks = <&clock_mmss MMSS_CAMSS_VFE1_CLK>,
+		 <&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>;
+	parent-supply = <&gdsc_camss_top>;
+	status = "ok";
+};
+
+&gdsc_cpp {
+	clock-names = "core_clk";
+	clocks = <&clock_mmss MMSS_CAMSS_CPP_CLK>;
+	parent-supply = <&gdsc_camss_top>;
+	status = "ok";
+};
+
+&gdsc_mdss {
+	clock-names = "bus_clk", "rot_clk";
+	clocks = <&clock_mmss MMSS_MDSS_AXI_CLK>,
+		 <&clock_mmss MMSS_MDSS_ROT_CLK>;
+	proxy-supply = <&gdsc_mdss>;
+	qcom,proxy-consumer-enable;
+	status = "ok";
+};
+
+&gdsc_gpu_gx {
+	clock-names = "bimc_core_clk", "core_clk", "core_root_clk";
+	clocks = <&clock_gcc GCC_GPU_BIMC_GFX_CLK>,
+		 <&clock_gfx GPUCC_GFX3D_CLK>,
+		 <&clock_gfx GFX3D_CLK_SRC>;
+	qcom,force-enable-root-clk;
+	parent-supply = <&gfx_vreg_corner>;
+	status = "ok";
+};
+
+&gdsc_gpu_cx {
+	status = "ok";
+};