diff options
| author | Osvaldo Banuelos <osvaldob@codeaurora.org> | 2016-06-22 14:33:29 -0700 |
|---|---|---|
| committer | Kyle Yan <kyan@codeaurora.org> | 2016-06-24 15:04:49 -0700 |
| commit | a26ae43d87f17437319b0a2f5e30b9f79ad18950 (patch) | |
| tree | 8c2465b684968a60df8910d5e37228f508b7ecf6 /arch | |
| parent | 506ddf3b445f5392f01d3ea2aeff782ae4ef0b37 (diff) | |
ARM: dts: msm: add CPR panic register configuration for msmcobalt
Specify the panic register configuration in the VDD_APC0
and VDD_APC1 CPR device nodes. This enables the CPR panic
handler to dump the values of the specified registers during
a kernel panic.
CRs-Fixed: 1033060
Change-Id: Ifdd03f27ed1135acd4470d891e1b5aca4a11dd65
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi index 7dc276bb5fdb..21dbb8143061 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-regulator.dtsi @@ -614,6 +614,11 @@ qcom,cpr-enable; qcom,cpr-hw-closed-loop; + qcom,cpr-panic-reg-addr-list = + <0x179cbaa4 0x17912c18>; + qcom,cpr-panic-reg-name-list = + "PWR_CPRH_STATUS", "APCLUS0_L2_SAW4_PMIC_STS"; + thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; @@ -770,6 +775,11 @@ qcom,cpr-enable; qcom,cpr-hw-closed-loop; + qcom,cpr-panic-reg-addr-list = + <0x179c7aa4 0x17812c18>; + qcom,cpr-panic-reg-name-list = + "PERF_CPRH_STATUS", "APCLUS1_L2_SAW4_PMIC_STS"; + thread@0 { qcom,cpr-thread-id = <0>; qcom,cpr-consecutive-up = <0>; |