diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2017-03-21 13:28:20 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-03-21 13:28:20 -0700 |
| commit | c37da11cca8324d6505d5bcbc8f8aedcb237790c (patch) | |
| tree | 19d8abc4d91b2fb6763ba08b03cf9aa554f3410c /arch | |
| parent | 96e7b02651276873d4e1e6ed532c32e0337ff492 (diff) | |
| parent | d3e47e331617af3c87138bd205e65c6fa1a1bca7 (diff) | |
Merge "msm: camera: Add regulator enable and disable in csiphy"
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8996-camera.dtsi | 38 |
1 files changed, 28 insertions, 10 deletions
diff --git a/arch/arm/boot/dts/qcom/msm8996-camera.dtsi b/arch/arm/boot/dts/qcom/msm8996-camera.dtsi index ec713e1b11fd..3ffd74e15f32 100644 --- a/arch/arm/boot/dts/qcom/msm8996-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-camera.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,18 +28,24 @@ reg-names = "csiphy", "csiphy_clk_mux"; interrupts = <0 78 0>; interrupt-names = "csiphy"; - clocks = <&clock_mmss clk_camss_top_ahb_clk>, + qcom,csi-vdd-voltage = <1250000>; + qcom,mipi-csi-vdd-supply = <&pm8994_l2>; + mmagic-supply = <&gdsc_mmagic_camss>; + gdscr-supply = <&gdsc_camss_top>; + qcom,cam-vreg-name = "mmagic", "gdscr"; + clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, + <&clock_mmss clk_camss_top_ahb_clk>, <&clock_mmss clk_camss_ispif_ahb_clk>, <&clock_mmss clk_csi0phytimer_clk_src>, <&clock_mmss clk_camss_csi0phytimer_clk>, <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_csiphy0_3p_clk_src>, <&clock_mmss clk_camss_csiphy0_3p_clk>; - clock-names = "camss_top_ahb_clk", + clock-names = "mmagic_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ahb_clk", "csiphy_3p_clk_src", "csi_phy_3p_clk"; - qcom,clock-rates = <0 0 200000000 0 0 100000000 0>; + qcom,clock-rates = <0 0 0 200000000 0 0 100000000 0>; }; qcom,csiphy@a35000 { @@ -49,18 +55,24 @@ reg-names = "csiphy", "csiphy_clk_mux"; interrupts = <0 79 0>; interrupt-names = "csiphy"; - clocks = <&clock_mmss clk_camss_top_ahb_clk>, + qcom,csi-vdd-voltage = <1250000>; + qcom,mipi-csi-vdd-supply = <&pm8994_l2>; + mmagic-supply = <&gdsc_mmagic_camss>; + gdscr-supply = <&gdsc_camss_top>; + qcom,cam-vreg-name = "mmagic", "gdscr"; + clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, + <&clock_mmss clk_camss_top_ahb_clk>, <&clock_mmss clk_camss_ispif_ahb_clk>, <&clock_mmss clk_csi1phytimer_clk_src>, <&clock_mmss clk_camss_csi1phytimer_clk>, <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_csiphy1_3p_clk_src>, <&clock_mmss clk_camss_csiphy1_3p_clk>; - clock-names = "camss_top_ahb_clk", + clock-names = "mmagic_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ahb_clk", "csiphy_3p_clk_src", "csi_phy_3p_clk"; - qcom,clock-rates = <0 0 200000000 0 0 100000000 0>; + qcom,clock-rates = <0 0 0 200000000 0 0 100000000 0>; }; qcom,csiphy@a36000 { @@ -70,18 +82,24 @@ reg-names = "csiphy", "csiphy_clk_mux"; interrupts = <0 80 0>; interrupt-names = "csiphy"; - clocks = <&clock_mmss clk_camss_top_ahb_clk>, + qcom,csi-vdd-voltage = <1250000>; + qcom,mipi-csi-vdd-supply = <&pm8994_l2>; + mmagic-supply = <&gdsc_mmagic_camss>; + gdscr-supply = <&gdsc_camss_top>; + qcom,cam-vreg-name = "mmagic", "gdscr"; + clocks = <&clock_mmss clk_mmss_mmagic_ahb_clk>, + <&clock_mmss clk_camss_top_ahb_clk>, <&clock_mmss clk_camss_ispif_ahb_clk>, <&clock_mmss clk_csi2phytimer_clk_src>, <&clock_mmss clk_camss_csi2phytimer_clk>, <&clock_mmss clk_camss_ahb_clk>, <&clock_mmss clk_csiphy2_3p_clk_src>, <&clock_mmss clk_camss_csiphy2_3p_clk>; - clock-names = "camss_top_ahb_clk", + clock-names = "mmagic_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ahb_clk", "csiphy_3p_clk_src", "csi_phy_3p_clk"; - qcom,clock-rates = <0 0 200000000 0 0 100000000 0>; + qcom,clock-rates = <0 0 0 200000000 0 0 100000000 0>; }; qcom,csid@a30000 { |