diff options
| author | Chandan Uddaraju <chandanu@codeaurora.org> | 2016-05-04 15:49:26 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-09 18:35:25 -0700 |
| commit | f0df83dc8b5057a545f267dbb0dfd622b67cac24 (patch) | |
| tree | 5e17935664753441038665841700ff2cd1db828f /arch | |
| parent | 0443c0f276fb0c96213ca0f771fcf9c8602ade92 (diff) | |
ARM: dts: msm: setup external clock sources for DP clock on msmcobalt
The DP RCGs exported by the MMSS clock controller (MMSS-CC)
can be sourced out of the DP PLL which is outside the MMSS-CC. Set up
these external clock sources to point to the DP PLL clocks.
CRs-Fixed: 1009740
Change-Id: Ia8f60ba711770c26e5b5919d2c39d7986403ece6
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 2bd480fe25bc..ea25b61c17be 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -631,14 +631,17 @@ vdd_dig-supply = <&pmcobalt_s1_level>; clock-names = "xo", "gpll0", "gpll0_div", "pclk0_src", "pclk1_src", - "byte0_src", "byte1_src"; + "byte0_src", "byte1_src", + "dp_link_src", "dp_vco_div"; clocks = <&clock_gcc clk_cxo_clk_src>, <&clock_gcc clk_gpll0_out_main>, <&clock_gcc clk_gcc_mmss_gpll0_div_clk>, <&mdss_dsi0_pll clk_dsi0pll_pclk_mux>, <&mdss_dsi1_pll clk_dsi1pll_pclk_mux>, <&mdss_dsi0_pll clk_dsi0pll_byteclk_mux>, - <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>; + <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>, + <&mdss_dp_pll clk_dp_link_2x_clk_mux>, + <&mdss_dp_pll clk_vco_divided_clk_src>; #clock-cells = <1>; }; |