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authorChris Wilson <chris@chris-wilson.co.uk>2010-09-14 20:15:22 +0100
committerChris Wilson <chris@chris-wilson.co.uk>2010-09-14 21:13:13 +0100
commit3f08e4ef807c3103ceebf7993c7463c7a90646f3 (patch)
tree63119dac1d44e097fd8cbcaa3f77eb111757483e /drivers/char/agp
parentb1c5b0f8cc16a1d22e2e521c4236a6ceca1b2983 (diff)
agp/intel: Fix resume regression from 2d2430cf
On i915 [EeePCs] something scribles over the registers during suspend and resume so we must save a copy of the PGETBL_CTL register programmed by the BIOS and restore that upon resume. Reported-by: Sitsofe Wheeler <sitsofe@yahoo.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/char/agp')
-rw-r--r--drivers/char/agp/intel-gtt.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 791582c73ff7..ebdeab26ee3c 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -98,6 +98,7 @@ static struct _intel_private {
u8 __iomem *registers;
phys_addr_t gtt_bus_addr;
phys_addr_t gma_bus_addr;
+ phys_addr_t pte_bus_addr;
u32 __iomem *gtt; /* I915G */
int num_dcache_entries;
union {
@@ -896,11 +897,9 @@ static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
static void intel_enable_gtt(void)
{
- u32 ptetbl_addr, gma_addr;
+ u32 gma_addr;
u16 gmch_ctrl;
- ptetbl_addr = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
-
if (INTEL_GTT_GEN == 2)
pci_read_config_dword(intel_private.pcidev, I810_GMADDR,
&gma_addr);
@@ -914,7 +913,8 @@ static void intel_enable_gtt(void)
gmch_ctrl |= I830_GMCH_ENABLED;
pci_write_config_word(intel_private.bridge_dev, I830_GMCH_CTRL, gmch_ctrl);
- writel(ptetbl_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
+ writel(intel_private.pte_bus_addr|I810_PGETBL_ENABLED,
+ intel_private.registers+I810_PGETBL_CTL);
readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
}
@@ -930,6 +930,8 @@ static int i830_setup(void)
return -ENOMEM;
intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE;
+ intel_private.pte_bus_addr =
+ readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
intel_i830_setup_flush();
@@ -1279,6 +1281,7 @@ static int i9xx_setup(void)
if (INTEL_GTT_GEN == 3) {
u32 gtt_addr;
+
pci_read_config_dword(intel_private.pcidev,
I915_PTEADDR, &gtt_addr);
intel_private.gtt_bus_addr = gtt_addr;
@@ -1298,6 +1301,9 @@ static int i9xx_setup(void)
intel_private.gtt_bus_addr = reg_addr + gtt_offset;
}
+ intel_private.pte_bus_addr =
+ readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
+
intel_i9xx_setup_flush();
return 0;