diff options
| author | Paul Cercueil <paul@crapouillou.net> | 2019-01-27 23:09:20 -0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2019-03-23 08:44:36 +0100 |
| commit | 96ad35532ccc3353c56800b4e4b0f020eca82344 (patch) | |
| tree | c58813ab1bb82144d3b8a34d393b7c5fdd58a9ba /drivers/clk/clk-ls1x.c | |
| parent | 64847df5bff163f4f0ded9dd29b0e9d8ce8832c6 (diff) | |
clk: ingenic: Fix round_rate misbehaving with non-integer dividers
commit bc5d922c93491878c44c9216e9d227c7eeb81d7f upstream.
Take a parent rate of 180 MHz, and a requested rate of 4.285715 MHz.
This results in a theorical divider of 41.999993 which is then rounded
up to 42. The .round_rate function would then return (180 MHz / 42) as
the clock, rounded down, so 4.285714 MHz.
Calling clk_set_rate on 4.285714 MHz would round the rate again, and
give a theorical divider of 42,0000028, now rounded up to 43, and the
rate returned would be (180 MHz / 43) which is 4.186046 MHz, aka. not
what we requested.
Fix this by rounding up the divisions.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Maarten ter Huurne <maarten@treewalker.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/clk/clk-ls1x.c')
0 files changed, 0 insertions, 0 deletions