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| author | Abhinav Kumar <abhinavk@codeaurora.org> | 2017-02-24 11:56:21 -0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-04-05 16:48:34 -0700 |
| commit | 3a757d0376ff8f63b894fe129c6dc02755a9add8 (patch) | |
| tree | 5d3f848f3678b0645ffdc221d000d83127319df8 /drivers/clk/meson | |
| parent | b2e934426e075085395a04261280ca0b05547e89 (diff) | |
clk: mdss: adjust PLL disable sequence to avoid glitch
Adjust the PLL disable sequence as per the latest HW
programming guidelines to ensure there will not be any
stray clock glitches when PLL is turned OFF abruptly.
Change-Id: I6df35bbe18b0c42b43f38b9dd85c3502b2038928
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Diffstat (limited to 'drivers/clk/meson')
0 files changed, 0 insertions, 0 deletions