diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-05-10 16:29:54 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-15 22:41:21 -0700 |
| commit | 8cc9b35f9afa15b9aa45c7fc35ddcd958d3207cb (patch) | |
| tree | a30290d771b59d24c37ca56a0e8db68886955ea5 /drivers/clk/msm | |
| parent | 4622a2f4260b7d6a523909a4d86fa66000f36324 (diff) | |
clk: msm: clock-gcc-cobalt: Add reset capability to PCIE pipe clock
Instead of having a separate reset clock for PCIE 0 reset, tag the
BCR register with the gcc_pcie_0_pipe_clk directly.
CRs-Fixed: 1014989
Change-Id: Icbc3a4a237bd0ac75fbef0857238e18cfb0ca533
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'drivers/clk/msm')
| -rw-r--r-- | drivers/clk/msm/clock-gcc-cobalt.c | 22 |
1 files changed, 6 insertions, 16 deletions
diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c index 3e2eb0dbc2bf..e9af651e9deb 100644 --- a/drivers/clk/msm/clock-gcc-cobalt.c +++ b/drivers/clk/msm/clock-gcc-cobalt.c @@ -1070,16 +1070,6 @@ static struct branch_clk gcc_hdmi_clkref_clk = { }, }; -static struct reset_clk gcc_pcie_0_phy_reset = { - .reset_reg = GCC_PCIE_0_PHY_BCR, - .base = &virt_base, - .c = { - .dbg_name = "gcc_pcie_0_phy_reset", - .ops = &clk_ops_rst, - CLK_INIT(gcc_pcie_0_phy_reset.c), - }, -}; - static struct branch_clk gcc_pcie_clkref_clk = { .cbcr_reg = GCC_PCIE_CLKREF_EN, .has_sibling = 1, @@ -1802,14 +1792,15 @@ static struct branch_clk gcc_pcie_0_mstr_axi_clk = { }, }; -static struct gate_clk gcc_pcie_0_pipe_clk = { - .en_reg = GCC_PCIE_0_PIPE_CBCR, - .en_mask = BIT(0), - .delay_us = 500, +static struct branch_clk gcc_pcie_0_pipe_clk = { + .cbcr_reg = GCC_PCIE_0_PIPE_CBCR, + .bcr_reg = GCC_PCIE_0_PHY_BCR, + .has_sibling = 1, + .halt_check = DELAY, .base = &virt_base, .c = { .dbg_name = "gcc_pcie_0_pipe_clk", - .ops = &clk_ops_gate, + .ops = &clk_ops_branch, CLK_INIT(gcc_pcie_0_pipe_clk.c), }, }; @@ -2611,7 +2602,6 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(usb3_phy_aux_clk_src), CLK_LIST(hmss_gpll0_clk_src), CLK_LIST(qspi_ref_clk_src), - CLK_LIST(gcc_pcie_0_phy_reset), CLK_LIST(gcc_usb3_phy_reset), CLK_LIST(gcc_usb3phy_phy_reset), CLK_LIST(gcc_qusb2phy_prim_reset), |