diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-02-09 17:27:55 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:20:24 -0700 |
| commit | 96da03ab3132bc039d414c103d1e27e2e45f063e (patch) | |
| tree | 2af8bf7d3656727e64d15d87dc6bf3bce3a46be2 /drivers/clk/msm | |
| parent | d5d3df187e6667b626a5e7ff4b1b146956834fde (diff) | |
clk: msm: clock-gpu-cobalt: Correct the CRC enable sequence
The GPU GDSCs need to be turned prior to enabling the graphics
clock and programming the CRC registers. Add that support.
CRs-Fixed: 974342
Change-Id: I4f97c10c383f79490c8dc428ef5ffb1040adc18d
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'drivers/clk/msm')
| -rw-r--r-- | drivers/clk/msm/clock-gpu-cobalt.c | 50 |
1 files changed, 32 insertions, 18 deletions
diff --git a/drivers/clk/msm/clock-gpu-cobalt.c b/drivers/clk/msm/clock-gpu-cobalt.c index f28f6cbaef26..c98943e5ff37 100644 --- a/drivers/clk/msm/clock-gpu-cobalt.c +++ b/drivers/clk/msm/clock-gpu-cobalt.c @@ -39,7 +39,11 @@ static void __iomem *virt_base; #define gpu_pll0_pll_out_even_source_val 1 #define gpu_pll0_pll_out_odd_source_val 2 -#define CRC_MND_CFG_OFFSET 0x4 +#define SW_COLLAPSE_MASK BIT(0) +#define GPU_CX_GDSCR_OFFSET 0x1004 +#define GPU_GX_GDSCR_OFFSET 0x1094 +#define CRC_SID_FSM_OFFSET 0x10A0 +#define CRC_MND_CFG_OFFSET 0x10A4 #define F(f, s, div, m, n) \ { \ @@ -395,7 +399,6 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) { struct resource *res; struct device_node *of_node = pdev->dev.of_node; - void __iomem *crc_sid_fsm_ctrl; int rc; struct regulator *reg; u32 regval; @@ -413,19 +416,6 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) return -ENOMEM; } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crc_sid_fsm"); - if (!res) { - dev_err(&pdev->dev, "Unable to retrieve crc_sid_fsm base\n"); - return -ENOMEM; - } - - crc_sid_fsm_ctrl = devm_ioremap(&pdev->dev, res->start, - resource_size(res)); - if (!crc_sid_fsm_ctrl) { - dev_err(&pdev->dev, "Failed to map crc_sid_fsm_ctrl\n"); - return -ENOMEM; - } - reg = vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); if (IS_ERR(reg)) { if (PTR_ERR(reg) != -EPROBE_DEFER) @@ -501,14 +491,38 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) clk_prepare_enable(&gpucc_cxo_clk.c); /* CRC ENABLE SEQUENCE */ - clk_set_rate(&gpucc_gfx3d_clk.c, 650000000); + clk_set_rate(&gpucc_gfx3d_clk.c, 251000000); + /* Turn on the gpu_cx and gpu_gx GDSCs */ + regval = readl_relaxed(virt_base + GPU_CX_GDSCR_OFFSET); + regval &= ~SW_COLLAPSE_MASK; + writel_relaxed(regval, virt_base + GPU_CX_GDSCR_OFFSET); + /* Wait for 10usecs to let the GDSC turn ON */ + mb(); + udelay(10); + regval = readl_relaxed(virt_base + GPU_GX_GDSCR_OFFSET); + regval &= ~SW_COLLAPSE_MASK; + writel_relaxed(regval, virt_base + GPU_GX_GDSCR_OFFSET); + /* Wait for 10usecs to let the GDSC turn ON */ + mb(); + udelay(10); + /* Enable the graphics clock */ clk_prepare_enable(&gpucc_gfx3d_clk.c); /* Enabling MND RC in Bypass mode */ - writel_relaxed(0x00015010, crc_sid_fsm_ctrl + CRC_MND_CFG_OFFSET); - writel_relaxed(0x00800000, crc_sid_fsm_ctrl); + writel_relaxed(0x00015010, virt_base + CRC_MND_CFG_OFFSET); + writel_relaxed(0x00800000, virt_base + CRC_SID_FSM_OFFSET); /* Wait for 16 cycles before continuing */ udelay(1); + clk_set_rate(&gpucc_gfx3d_clk.c, 650000000); + /* Disable the graphics clock */ clk_disable_unprepare(&gpucc_gfx3d_clk.c); + /* Turn off the gpu_cx and gpu_gx GDSCs */ + regval = readl_relaxed(virt_base + GPU_GX_GDSCR_OFFSET); + regval |= SW_COLLAPSE_MASK; + writel_relaxed(regval, virt_base + GPU_GX_GDSCR_OFFSET); + regval = readl_relaxed(virt_base + GPU_CX_GDSCR_OFFSET); + regval |= SW_COLLAPSE_MASK; + writel_relaxed(regval, virt_base + GPU_CX_GDSCR_OFFSET); + /* END OF CRC ENABLE SEQUENCE */ /* * Force periph logic to be ON since after NAP, the value of the perf |