diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-05-03 11:53:02 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-10 13:20:08 -0700 |
| commit | c42d0bb4ffb40ede918484e4510fa75b05424058 (patch) | |
| tree | 74a79d717cd07b236ddfb4f3be1e99be5d216502 /drivers/clk/msm | |
| parent | 8516d6c280090c4579f72101c89e262b3dda5722 (diff) | |
clk: msm: clock-gcc-cobalt: Add new hw_ctl_clk type UFS clocks
Add new UFS clocks to support enabling/disabling the hardware
dynamic gating for their corresponding branch clocks.
CRs-Fixed: 1012355
Change-Id: I4836ad8a775b0ec0375e37d27fcbe380e661a7b2
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'drivers/clk/msm')
| -rw-r--r-- | drivers/clk/msm/clock-gcc-cobalt.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c index 615faecc6379..7c17ef357165 100644 --- a/drivers/clk/msm/clock-gcc-cobalt.c +++ b/drivers/clk/msm/clock-gcc-cobalt.c @@ -1996,6 +1996,17 @@ static struct branch_clk gcc_ufs_axi_clk = { }, }; +static struct hw_ctl_clk gcc_ufs_axi_hw_ctl_clk = { + .cbcr_reg = GCC_UFS_AXI_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_axi_hw_ctl_clk", + .parent = &gcc_ufs_axi_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_ufs_axi_hw_ctl_clk.c), + }, +}; + static struct branch_clk gcc_ufs_ice_core_clk = { .cbcr_reg = GCC_UFS_ICE_CORE_CBCR, .has_sibling = 0, @@ -2008,6 +2019,17 @@ static struct branch_clk gcc_ufs_ice_core_clk = { }, }; +static struct hw_ctl_clk gcc_ufs_ice_core_hw_ctl_clk = { + .cbcr_reg = GCC_UFS_ICE_CORE_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_ice_core_hw_ctl_clk", + .parent = &gcc_ufs_ice_core_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_ufs_ice_core_hw_ctl_clk.c), + }, +}; + static struct branch_clk gcc_ufs_phy_aux_clk = { .cbcr_reg = GCC_UFS_PHY_AUX_CBCR, .has_sibling = 0, @@ -2020,6 +2042,17 @@ static struct branch_clk gcc_ufs_phy_aux_clk = { }, }; +static struct hw_ctl_clk gcc_ufs_phy_aux_hw_ctl_clk = { + .cbcr_reg = GCC_UFS_PHY_AUX_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_phy_aux_hw_ctl_clk", + .parent = &gcc_ufs_phy_aux_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_ufs_phy_aux_hw_ctl_clk.c), + }, +}; + static struct gate_clk gcc_ufs_rx_symbol_0_clk = { .en_reg = GCC_UFS_RX_SYMBOL_0_CBCR, .en_mask = BIT(0), @@ -2068,6 +2101,17 @@ static struct branch_clk gcc_ufs_unipro_core_clk = { }, }; +static struct hw_ctl_clk gcc_ufs_unipro_core_hw_ctl_clk = { + .cbcr_reg = GCC_UFS_UNIPRO_CORE_CBCR, + .base = &virt_base, + .c = { + .dbg_name = "gcc_ufs_unipro_core_hw_ctl_clk", + .parent = &gcc_ufs_unipro_core_clk.c, + .ops = &clk_ops_branch_hw_ctl, + CLK_INIT(gcc_ufs_unipro_core_hw_ctl_clk.c), + }, +}; + static struct branch_clk gcc_usb30_master_clk = { .cbcr_reg = GCC_USB30_MASTER_CBCR, .bcr_reg = GCC_USB_30_BCR, @@ -2642,12 +2686,16 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_tsif_ref_clk), CLK_LIST(gcc_ufs_ahb_clk), CLK_LIST(gcc_ufs_axi_clk), + CLK_LIST(gcc_ufs_axi_hw_ctl_clk), CLK_LIST(gcc_ufs_ice_core_clk), + CLK_LIST(gcc_ufs_ice_core_hw_ctl_clk), CLK_LIST(gcc_ufs_phy_aux_clk), + CLK_LIST(gcc_ufs_phy_aux_hw_ctl_clk), CLK_LIST(gcc_ufs_rx_symbol_0_clk), CLK_LIST(gcc_ufs_rx_symbol_1_clk), CLK_LIST(gcc_ufs_tx_symbol_0_clk), CLK_LIST(gcc_ufs_unipro_core_clk), + CLK_LIST(gcc_ufs_unipro_core_hw_ctl_clk), CLK_LIST(gcc_usb30_master_clk), CLK_LIST(gcc_usb30_mock_utmi_clk), CLK_LIST(gcc_usb30_sleep_clk), |