diff options
| author | Casey Piper <cpiper@codeaurora.org> | 2015-06-10 15:37:24 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:42:58 -0700 |
| commit | fc534490e0fa44936505876a983152d608aecba0 (patch) | |
| tree | 2c6eb7c8e3b1004fd349205aadd88b090e5f7c16 /drivers/clk/msm | |
| parent | 466f6c1dbe257752b5437ae6709de5dd36f11857 (diff) | |
clk: msm: mdss: update HDMI PLL locking sequence for MSM8996v1
Update SVS mode and driver level settings for
MSM8996v1 PLL locking sequence, based on Si
characterization.
Change-Id: Ic25e89f62b222847eef491a1c4138434ab2b38fe
Signed-off-by: Casey Piper <cpiper@codeaurora.org>
Diffstat (limited to 'drivers/clk/msm')
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c | 61 |
1 files changed, 41 insertions, 20 deletions
diff --git a/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c b/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c index 921ffad4f38b..682586a53526 100644 --- a/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c +++ b/drivers/clk/msm/mdss/mdss-hdmi-pll-8996.c @@ -738,7 +738,8 @@ static int hdmi_8996_v1_calculate(u32 pix_clk, cfg->com_restrim_ctrl = 0x0; cfg->com_vco_tune_ctrl = 0x1C; - cfg->com_svs_mode_clk_sel = 0; + cfg->com_svs_mode_clk_sel = + (bclk >= HDMI_DIG_FREQ_BIT_CLK_THRESHOLD ? 1 : 2); cfg->com_hsclk_sel = (0x28 | hsclk); cfg->com_pll_cctrl_mode0 = cctrl; cfg->com_pll_rctrl_mode0 = rctrl; @@ -756,14 +757,14 @@ static int hdmi_8996_v1_calculate(u32 pix_clk, cfg->com_coreclk_div = HDMI_CORECLK_DIV; if (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) { - cfg->tx_l0_tx_drv_lvl = 0x39; - cfg->tx_l0_tx_emp_post1_lvl = 0x33; - cfg->tx_l1_tx_drv_lvl = 0x39; - cfg->tx_l1_tx_emp_post1_lvl = 0x33; - cfg->tx_l2_tx_drv_lvl = 0x39; - cfg->tx_l2_tx_emp_post1_lvl = 0x33; - cfg->tx_l3_tx_drv_lvl = 0x39; - cfg->tx_l3_tx_emp_post1_lvl = 0x30; + cfg->tx_l0_tx_drv_lvl = 0x25; + cfg->tx_l0_tx_emp_post1_lvl = 0x23; + cfg->tx_l1_tx_drv_lvl = 0x25; + cfg->tx_l1_tx_emp_post1_lvl = 0x23; + cfg->tx_l2_tx_drv_lvl = 0x25; + cfg->tx_l2_tx_emp_post1_lvl = 0x23; + cfg->tx_l3_tx_drv_lvl = 0x22; + cfg->tx_l3_tx_emp_post1_lvl = 0x27; cfg->tx_l0_vmode_ctrl1 = 0x00; cfg->tx_l0_vmode_ctrl2 = 0x0D; cfg->tx_l1_vmode_ctrl1 = 0x00; @@ -771,16 +772,17 @@ static int hdmi_8996_v1_calculate(u32 pix_clk, cfg->tx_l2_vmode_ctrl1 = 0x00; cfg->tx_l2_vmode_ctrl2 = 0x0D; cfg->tx_l3_vmode_ctrl1 = 0x00; - cfg->tx_l3_vmode_ctrl2 = 0x0D; - } else { - cfg->tx_l0_tx_drv_lvl = 0x35; - cfg->tx_l0_tx_emp_post1_lvl = 0x30; - cfg->tx_l1_tx_drv_lvl = 0x35; - cfg->tx_l1_tx_emp_post1_lvl = 0x30; - cfg->tx_l2_tx_drv_lvl = 0x35; - cfg->tx_l2_tx_emp_post1_lvl = 0x30; - cfg->tx_l3_tx_drv_lvl = 0x35; - cfg->tx_l3_tx_emp_post1_lvl = 0x30; + cfg->tx_l3_vmode_ctrl2 = 0x00; + cfg->com_restrim_ctrl = 0x0; + } else if (bclk > HDMI_MID_FREQ_BIT_CLK_THRESHOLD) { + cfg->tx_l0_tx_drv_lvl = 0x25; + cfg->tx_l0_tx_emp_post1_lvl = 0x23; + cfg->tx_l1_tx_drv_lvl = 0x25; + cfg->tx_l1_tx_emp_post1_lvl = 0x23; + cfg->tx_l2_tx_drv_lvl = 0x25; + cfg->tx_l2_tx_emp_post1_lvl = 0x23; + cfg->tx_l3_tx_drv_lvl = 0x25; + cfg->tx_l3_tx_emp_post1_lvl = 0x23; cfg->tx_l0_vmode_ctrl1 = 0x00; cfg->tx_l0_vmode_ctrl2 = 0x0D; cfg->tx_l1_vmode_ctrl1 = 0x00; @@ -788,7 +790,26 @@ static int hdmi_8996_v1_calculate(u32 pix_clk, cfg->tx_l2_vmode_ctrl1 = 0x00; cfg->tx_l2_vmode_ctrl2 = 0x0D; cfg->tx_l3_vmode_ctrl1 = 0x00; - cfg->tx_l3_vmode_ctrl2 = 0x0D; + cfg->tx_l3_vmode_ctrl2 = 0x00; + cfg->com_restrim_ctrl = 0x0; + } else { + cfg->tx_l0_tx_drv_lvl = 0x20; + cfg->tx_l0_tx_emp_post1_lvl = 0x20; + cfg->tx_l1_tx_drv_lvl = 0x20; + cfg->tx_l1_tx_emp_post1_lvl = 0x20; + cfg->tx_l2_tx_drv_lvl = 0x20; + cfg->tx_l2_tx_emp_post1_lvl = 0x20; + cfg->tx_l3_tx_drv_lvl = 0x20; + cfg->tx_l3_tx_emp_post1_lvl = 0x20; + cfg->tx_l0_vmode_ctrl1 = 0x00; + cfg->tx_l0_vmode_ctrl2 = 0x0E; + cfg->tx_l1_vmode_ctrl1 = 0x00; + cfg->tx_l1_vmode_ctrl2 = 0x0E; + cfg->tx_l2_vmode_ctrl1 = 0x00; + cfg->tx_l2_vmode_ctrl2 = 0x0E; + cfg->tx_l3_vmode_ctrl1 = 0x00; + cfg->tx_l3_vmode_ctrl2 = 0x0E; + cfg->com_restrim_ctrl = 0xD8; } cfg->phy_mode = (bclk > HDMI_HIGH_FREQ_BIT_CLK_THRESHOLD) ? 0x10 : 0x0; |