clk: qcom: rpmcc: Add rpm clock data for msm8996

Add all RPM clock data for msm8996 family of devices

ToDo: Adapt to changes needed for RPM over GLINK against
RPM over SMD that the driver currently supports

Change-Id: Ib095af601a4f03d866cf94c8e277d04630abb42b
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>

1 files changed, 75 insertions, 0 deletions

diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index adfb58f51351..2a6f9a6ee232 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -462,8 +462,83 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
 	.num_clks = ARRAY_SIZE(msm8916_clks),
 };
 
+/* msm8996 */
+DEFINE_CLK_SMD_RPM(msm8996, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8996, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
+DEFINE_CLK_SMD_RPM(msm8996, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
+DEFINE_CLK_SMD_RPM(msm8996, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8996, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
+		   QCOM_SMD_RPM_MMAXI_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8996, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8996, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
+DEFINE_CLK_SMD_RPM_BRANCH(msm8996, cxo, cxo_a, QCOM_SMD_RPM_MISC_CLK, 0, 19200000);
+DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre1_noc_clk, aggre1_noc_a_clk,
+			  QCOM_SMD_RPM_AGGR_CLK, 0, 1000);
+DEFINE_CLK_SMD_RPM_BRANCH(msm8996, aggre2_noc_clk, aggre2_noc_a_clk,
+			  QCOM_SMD_RPM_AGGR_CLK, 1, 1000);
+DEFINE_CLK_SMD_RPM_QDSS(msm8996, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk1, bb_clk1_a, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, bb_clk2, bb_clk2_a, 2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk1, rf_clk1_a, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, rf_clk2, rf_clk2_a, 5);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, ln_bb_clk, ln_bb_a_clk, 8);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk1, div_clk1_ao, 0xb);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk2, div_clk2_ao, 0xc);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8996, div_clk3, div_clk3_ao, 0xc);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk1_pin, bb_clk1_a_pin, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, bb_clk2_pin, bb_clk2_a_pin, 2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk1_pin, rf_clk1_a_pin, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8996, rf_clk2_pin, rf_clk2_a_pin, 5);
+
+static struct clk_smd_rpm *msm8996_clks[] = {
+	[RPM_XO_CLK_SRC] = &msm8996_cxo,
+	[RPM_XO_A_CLK_SRC] = &msm8996_cxo_a,
+	[RPM_AGGR1_NOC_CLK] = &msm8996_aggre1_noc_clk,
+	[RPM_AGGR1_NOC_A_CLK] = &msm8996_aggre1_noc_a_clk,
+	[RPM_AGGR2_NOC_CLK] = &msm8996_aggre2_noc_clk,
+	[RPM_AGGR2_NOC_A_CLK] = &msm8996_aggre2_noc_a_clk,
+	[RPM_PCNOC_CLK] = &msm8996_pcnoc_clk,
+	[RPM_PCNOC_A_CLK] = &msm8996_pcnoc_a_clk,
+	[RPM_SNOC_CLK] = &msm8996_snoc_clk,
+	[RPM_SNOC_A_CLK] = &msm8996_snoc_a_clk,
+	[RPM_CNOC_CLK] = &msm8996_cnoc_clk,
+	[RPM_CNOC_A_CLK] = &msm8996_cnoc_a_clk,
+	[RPM_BIMC_CLK] = &msm8996_bimc_clk,
+	[RPM_BIMC_A_CLK] = &msm8996_bimc_a_clk,
+	[RPM_MMAXI_CLK] = &msm8996_mmssnoc_axi_rpm_clk,
+	[RPM_MMAXI_A_CLK] = &msm8996_mmssnoc_axi_rpm_a_clk,
+	[RPM_IPA_CLK] = &msm8996_ipa_clk,
+	[RPM_IPA_A_CLK] = &msm8996_ipa_a_clk,
+	[RPM_CE1_CLK] = &msm8996_ce1_clk,
+	[RPM_CE1_A_CLK] = &msm8996_ce1_a_clk,
+	[RPM_QDSS_CLK] = &msm8996_qdss_clk,
+	[RPM_QDSS_A_CLK] = &msm8996_qdss_a_clk,
+	[RPM_LN_BB_CLK] = &msm8996_ln_bb_clk,
+	[RPM_LN_BB_A_CLK] = &msm8996_ln_bb_a_clk,
+	[RPM_DIV_CLK1] = &msm8996_div_clk1,
+	[RPM_DIV_CLK1_AO] = &msm8996_div_clk1_ao,
+	[RPM_DIV_CLK2] = &msm8996_div_clk2,
+	[RPM_DIV_CLK2_AO] = &msm8996_div_clk2_ao,
+	[RPM_DIV_CLK3] = &msm8996_div_clk3,
+	[RPM_DIV_CLK3_AO] = &msm8996_div_clk3_ao,
+	[RPM_BB_CLK1_PIN] = &msm8996_bb_clk1_pin,
+	[RPM_BB_CLK1_A_PIN] = &msm8996_bb_clk1_a_pin,
+	[RPM_BB_CLK2_PIN] = &msm8996_bb_clk2_pin,
+	[RPM_BB_CLK2_A_PIN] = &msm8996_bb_clk2_a_pin,
+	[RPM_RF_CLK1_PIN] = &msm8996_rf_clk1_pin,
+	[RPM_RF_CLK1_A_PIN] = &msm8996_rf_clk1_a_pin,
+	[RPM_RF_CLK2_PIN] = &msm8996_rf_clk2_pin,
+	[RPM_RF_CLK2_A_PIN] = &msm8996_rf_clk2_a_pin,
+};
+
+static const struct rpm_smd_clk_desc rpm_clk_msm8996 = {
+	.clks = msm8996_clks,
+	.num_clks = ARRAY_SIZE(msm8996_clks),
+};
+
 static const struct of_device_id rpm_smd_clk_match_table[] = {
 	{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916},
+	{ .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);