diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-01-27 16:48:14 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:19:38 -0700 |
| commit | 20c5a70a258c5b8e0db5d964fb2915a180a88b25 (patch) | |
| tree | c45f1f9aa823ed8488c98cbdc8393885b65b095d /drivers/clk | |
| parent | 73f564a2c281bbdc2223cea9cf3bd9fca856ca29 (diff) | |
clk: msm: clock-gpu-cobalt: Add the CRC programming sequence
The clock ramp controller helps in mitigating PDN droop during
low power use cases. Add the sequence to enable it in the clock
driver.
CRs-Fixed: 942848
Change-Id: Ia9afcd6492ddb38e3371a469c15ea07143c3c358
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/clock-gpu-cobalt.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/clk/msm/clock-gpu-cobalt.c b/drivers/clk/msm/clock-gpu-cobalt.c index 5c8994463151..c1bf686474db 100644 --- a/drivers/clk/msm/clock-gpu-cobalt.c +++ b/drivers/clk/msm/clock-gpu-cobalt.c @@ -39,6 +39,8 @@ static void __iomem *virt_base; #define gpu_pll0_pll_out_even_source_val 1 #define gpu_pll0_pll_out_odd_source_val 2 +#define CRC_MND_CFG_OFFSET 0x4 + #define F(f, s, div, m, n) \ { \ .freq_hz = (f), \ @@ -393,6 +395,7 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) { struct resource *res; struct device_node *of_node = pdev->dev.of_node; + void __iomem *crc_sid_fsm_ctrl; int rc; struct regulator *reg; u32 regval; @@ -410,6 +413,19 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) return -ENOMEM; } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "crc_sid_fsm"); + if (!res) { + dev_err(&pdev->dev, "Unable to retrieve crc_sid_fsm base\n"); + return -ENOMEM; + } + + crc_sid_fsm_ctrl = devm_ioremap(&pdev->dev, res->start, + resource_size(res)); + if (!crc_sid_fsm_ctrl) { + dev_err(&pdev->dev, "Failed to map crc_sid_fsm_ctrl\n"); + return -ENOMEM; + } + reg = vdd_dig.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_dig"); if (IS_ERR(reg)) { if (PTR_ERR(reg) != -EPROBE_DEFER) @@ -484,6 +500,16 @@ int msm_gpucc_cobalt_probe(struct platform_device *pdev) */ clk_prepare_enable(&gpucc_cxo_clk.c); + /* CRC ENABLE SEQUENCE */ + clk_set_rate(&gpucc_gfx3d_clk.c, 650000000); + clk_prepare_enable(&gpucc_gfx3d_clk.c); + /* Enabling MND RC in Bypass mode */ + writel_relaxed(0x00015010, crc_sid_fsm_ctrl + CRC_MND_CFG_OFFSET); + writel_relaxed(0x00800000, crc_sid_fsm_ctrl); + /* Wait for 16 cycles before continuing */ + udelay(1); + clk_disable_unprepare(&gpucc_gfx3d_clk.c); + dev_info(&pdev->dev, "Registered GPU clocks\n"); return 0; } |