diff options
| author | Kuogee Hsieh <khsieh@codeaurora.org> | 2015-04-15 13:47:01 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:41:46 -0700 |
| commit | 5223e55f1d8abb7cc8a8812b96a7b20de44ae2b5 (patch) | |
| tree | f12816347279f1cec1511a668086350bfb54198b /drivers/clk | |
| parent | 56c32840d45d088cee2d5f8fc948db6fa43eb36d (diff) | |
msm: mdss: fixed calculation of pll fractional divider
Pll unlocked due to wrong pll fractional divider calculated.
Pll fraction divider should be reminder of 2^20 after vco
rate divided by reference clock rate.
Change-Id: I9e4c2e3c0631e533d114c3e6acf65b71b9bf00d2
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c index 0a9aa8d37d78..7d812fc3e5bb 100644 --- a/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c +++ b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c @@ -348,7 +348,7 @@ static void pll_8996_dec_frac_calc(struct dsi_pll_db *pdb, vco_clk_rate, fref); dec_start_multiple = div_s64(vco_clk_rate * multiplier, fref); - div_s64_rem(vco_clk_rate * multiplier, fref, &div_frac_start); + div_s64_rem(dec_start_multiple, multiplier, &div_frac_start); dec_start = div_s64(dec_start_multiple, multiplier); @@ -535,7 +535,7 @@ static void pll_db_commit_8996(void __iomem *pll_base, data &= 0x0ff; MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START2, data); data = (pout->div_frac_start >> 16); - data &= 0x0ff; + data &= 0x0f; MDSS_PLL_REG_W(pll_base, DSIPHY_PLL_DIV_FRAC_START3, data); data = pout->plllock_cmp; @@ -652,7 +652,7 @@ unsigned long pll_vco_get_rate_8996(struct clk *c) pr_debug("dec_start = 0x%x\n", dec_start); div_frac_start = (MDSS_PLL_REG_R(pll->pll_base, - DSIPHY_PLL_DIV_FRAC_START3) & 0x0ff) << 16; + DSIPHY_PLL_DIV_FRAC_START3) & 0x0f) << 16; div_frac_start |= (MDSS_PLL_REG_R(pll->pll_base, DSIPHY_PLL_DIV_FRAC_START2) & 0x0ff) << 8; div_frac_start |= MDSS_PLL_REG_R(pll->pll_base, |