Merge "clk: msm: clock: Control the GPLL0 input sources to MMSSCC and GPUCC"

1 files changed, 49 insertions, 0 deletions

diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c
index 7299863ff42b..c539d57c0d0d 100644
--- a/drivers/clk/msm/clock-gcc-cobalt.c
+++ b/drivers/clk/msm/clock-gcc-cobalt.c
@@ -164,6 +164,20 @@ static struct pll_vote_clk gpll0_ao = {
 
 DEFINE_EXT_CLK(gpll0_out_main, &gpll0.c);
 
+static struct local_vote_clk gcc_mmss_gpll0_clk = {
+	.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.en_mask = BIT(1),
+	.base = &virt_base,
+	.halt_check = DELAY,
+	.c = {
+		.dbg_name = "gcc_mmss_gpll0_clk",
+		.parent = &gpll0.c,
+		.ops = &clk_ops_vote,
+		CLK_INIT(gcc_mmss_gpll0_clk.c),
+	},
+};
+
 static struct local_vote_clk gcc_mmss_gpll0_div_clk = {
 	.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
 	.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
@@ -178,6 +192,34 @@ static struct local_vote_clk gcc_mmss_gpll0_div_clk = {
 	},
 };
 
+static struct local_vote_clk gcc_gpu_gpll0_clk = {
+	.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.en_mask = BIT(4),
+	.base = &virt_base,
+	.halt_check = DELAY,
+	.c = {
+		.dbg_name = "gcc_gpu_gpll0_clk",
+		.parent = &gpll0.c,
+		.ops = &clk_ops_vote,
+		CLK_INIT(gcc_gpu_gpll0_clk.c),
+	},
+};
+
+static struct local_vote_clk gcc_gpu_gpll0_div_clk = {
+	.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.vote_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
+	.en_mask = BIT(3),
+	.base = &virt_base,
+	.halt_check = DELAY,
+	.c = {
+		.dbg_name = "gcc_gpu_gpll0_div_clk",
+		.parent = &gpll0.c,
+		.ops = &clk_ops_vote,
+		CLK_INIT(gcc_gpu_gpll0_div_clk.c),
+	},
+};
+
 static struct pll_vote_clk gpll4 = {
 	.en_reg = (void __iomem *)GCC_APCS_GPLL_ENA_VOTE,
 	.en_mask = BIT(4),
@@ -2535,7 +2577,10 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = {
 	CLK_LIST(gpll0),
 	CLK_LIST(gpll0_ao),
 	CLK_LIST(gpll0_out_main),
+	CLK_LIST(gcc_mmss_gpll0_clk),
 	CLK_LIST(gcc_mmss_gpll0_div_clk),
+	CLK_LIST(gcc_gpu_gpll0_clk),
+	CLK_LIST(gcc_gpu_gpll0_div_clk),
 	CLK_LIST(gpll4),
 	CLK_LIST(gpll4_out_main),
 	CLK_LIST(hmss_ahb_clk_src),
@@ -2784,6 +2829,10 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	/* Disable the GPLL0 active input to MMSS and GPU via MISC registers */
+	writel_relaxed(0x10003, virt_base + GCC_MMSS_MISC);
+	writel_relaxed(0x10003, virt_base + GCC_GPU_MISC);
+
 	/* Hold an active set vote for the cnoc_periph resource */
 	clk_set_rate(&cnoc_periph_keepalive_a_clk.c, 19200000);
 	clk_prepare_enable(&cnoc_periph_keepalive_a_clk.c);