diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-05-03 17:13:56 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-18 13:38:47 -0700 |
| commit | 85e3adb4575da5ddcd8b04b9d671ca5062b4528c (patch) | |
| tree | a5d1a0b43d014cb7acbbd5d61baec8f5532fbe36 /drivers/clk | |
| parent | d4202a685bb2ce236c244161b173b8cfc7aa7096 (diff) | |
clk: msm: clock-alpha-pll: Program the fabia PLL calibration register
Add programming the PLL_CAL_L_VAL register to the fabia PLL
set_rate sequence. This is required on MSMCOBALT v1 as a
workaround.
CRs-Fixed: 1016938
Change-Id: I298acf633228b2c565736bf7bfd446d96f4e1983
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/clock-alpha-pll.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/clk/msm/clock-alpha-pll.c b/drivers/clk/msm/clock-alpha-pll.c index a0dc22216364..0ef805364a05 100644 --- a/drivers/clk/msm/clock-alpha-pll.c +++ b/drivers/clk/msm/clock-alpha-pll.c @@ -53,6 +53,7 @@ #define FABIA_TEST_CTL_LO_REG(pll) (*pll->base + pll->offset + 0x1c) #define FABIA_TEST_CTL_HI_REG(pll) (*pll->base + pll->offset + 0x20) #define FABIA_L_REG(pll) (*pll->base + pll->offset + 0x4) +#define FABIA_CAL_L_VAL(pll) (*pll->base + pll->offset + 0x8) #define FABIA_FRAC_REG(pll) (*pll->base + pll->offset + 0x38) #define FABIA_PLL_OPMODE(pll) (*pll->base + pll->offset + 0x2c) @@ -963,6 +964,12 @@ static int fabia_alpha_pll_set_rate(struct clk *c, unsigned long rate) spin_lock_irqsave(&c->lock, flags); /* Set the new L value */ writel_relaxed(l_val, FABIA_L_REG(pll)); + /* + * pll_cal_l_val is set to pll_l_val on MOST targets. Set it + * explicitly here for PLL out-of-reset calibration to work + * without a glitch on all of them. + */ + writel_relaxed(l_val, FABIA_CAL_L_VAL(pll)); writel_relaxed(a_val, FABIA_FRAC_REG(pll)); alpha_pll_dynamic_update(pll); |