diff options
| author | Taniya Das <tdas@codeaurora.org> | 2017-03-06 16:13:59 +0530 |
|---|---|---|
| committer | Taniya Das <tdas@codeaurora.org> | 2017-03-06 16:14:09 +0530 |
| commit | 888f9aacd0f0761b0e86401fe3cfc46292ff2f80 (patch) | |
| tree | f5e45eebb6d860008b7f8f67460fe91163449aa4 /drivers/clk | |
| parent | 796d604a032ac3051e7879fcbf317c2edba7ba4e (diff) | |
clk: qcom: Update the source clock for 24MHz MCLK
The source clock of MMPLL10 has better jitter specs for MCLK than GPLL0_DIV
clock, so update the same to obtain 24MHz clock.
Change-Id: I57a77a83a5028c85d82fda4af53732f0bfb263e7
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/mmcc-sdm660.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c index 87e6f8c6be0a..0bf7ef05ed06 100644 --- a/drivers/clk/qcom/mmcc-sdm660.c +++ b/drivers/clk/qcom/mmcc-sdm660.c @@ -1041,7 +1041,7 @@ static const struct freq_tbl ftbl_mclk0_clk_src[] = { F(9600000, P_CXO, 2, 0, 0), F(16666667, P_GPLL0_OUT_MAIN_DIV, 2, 1, 9), F(19200000, P_CXO, 1, 0, 0), - F(24000000, P_GPLL0_OUT_MAIN_DIV, 1, 2, 25), + F(24000000, P_MMPLL10_PLL_OUT_MAIN, 1, 1, 24), F(33333333, P_GPLL0_OUT_MAIN_DIV, 1, 1, 9), F(48000000, P_GPLL0_OUT_MAIN, 1, 2, 25), F(66666667, P_GPLL0_OUT_MAIN, 1, 1, 9), |