diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2016-03-10 13:24:25 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-25 16:03:39 -0700 |
| commit | 8dc1ad3c55083e92dbe296d22e73959afad4f925 (patch) | |
| tree | 3eabc31774368fa00f0ebd2f9d6c6dedc751cbe4 /drivers/clk | |
| parent | 87c9c9ef950d8b353c7a60729961ea2140613024 (diff) | |
clk: msm: clock: Add support for programming the DCC AHB clock register
The gcc_dcc_ahb_clk needs to be controlled by the HLOS clock
driver on MSMCOBALT since its use is restricted to the HLOS
debug driver.
CRs-Fixed: 988930
Change-Id: I1abef9f1268080dbe5dba1e91f4b84fab03ce66c
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/clock-gcc-cobalt.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c index 978d06d769bb..24e7c048d1e7 100644 --- a/drivers/clk/msm/clock-gcc-cobalt.c +++ b/drivers/clk/msm/clock-gcc-cobalt.c @@ -2267,6 +2267,17 @@ static struct branch_clk gcc_mss_snoc_axi_clk = { }, }; +static struct branch_clk gcc_dcc_ahb_clk = { + .cbcr_reg = GCC_DCC_AHB_CBCR, + .has_sibling = 1, + .base = &virt_base, + .c = { + .dbg_name = "gcc_dcc_ahb_clk", + .ops = &clk_ops_branch, + CLK_INIT(gcc_dcc_ahb_clk.c), + }, +}; + static struct branch_clk hlos1_vote_lpass_core_smmu_clk = { .cbcr_reg = GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CBCR, .has_sibling = 0, @@ -2392,6 +2403,7 @@ static struct mux_clk gcc_debug_mux = { { &gcc_ufs_rx_symbol_0_clk.c, 0x00ed }, { &gcc_ufs_unipro_core_clk.c, 0x00f0 }, { &gcc_ufs_ice_core_clk.c, 0x00f1 }, + { &gcc_dcc_ahb_clk.c, 0x0119 }, { &ipa_clk.c, 0x011b }, { &gcc_mss_cfg_ahb_clk.c, 0x011f }, { &gcc_mss_q6_bimc_axi_clk.c, 0x0124 }, @@ -2647,6 +2659,7 @@ static struct clk_lookup msm_clocks_gcc_cobalt[] = { CLK_LIST(gcc_rx1_usb2_clkref_clk), CLK_LIST(gcc_ufs_clkref_clk), CLK_LIST(gcc_usb3_clkref_clk), + CLK_LIST(gcc_dcc_ahb_clk), CLK_LIST(hlos1_vote_lpass_core_smmu_clk), CLK_LIST(hlos1_vote_lpass_adsp_smmu_clk), }; |