diff options
| author | Dhaval Patel <pdhaval@codeaurora.org> | 2015-05-12 15:42:23 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:41:48 -0700 |
| commit | b262d770af3ed45b0cfa1eca2c600921e697b788 (patch) | |
| tree | ca0ef23533ad0f6dc53e6201338e393359836644 /drivers/clk | |
| parent | ef1fdddf22ab04a08472aec746892e23ba60aa04 (diff) | |
msm: mdss: fix pll stop sequence for msm8996 target
Turning off pll digital block before link clocks leads
to clock status stuck ON. Ideally, DSI driver should
first stop the lanes, followed by link clock stop
and pll disable. This change implements these
recommended sequence for both DSI controllers.
Change-Id: Ibe3061a65bad2dbfdffd9505d469f10f62a6e39d
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c index dbaafa7129db..23520971c507 100644 --- a/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c +++ b/drivers/clk/msm/mdss/mdss-dsi-pll-8996-util.c @@ -272,6 +272,7 @@ static void dsi_pll_disable(struct clk *c) { struct dsi_pll_vco_clk *vco = to_vco_clk(c); struct mdss_pll_resources *pll = vco->priv; + struct mdss_pll_resources *slave; if (!pll->pll_on && mdss_pll_resource_enable(pll, true)) { @@ -280,14 +281,25 @@ static void dsi_pll_disable(struct clk *c) } pll->handoff_resources = false; + slave = pll->slave; dsi_pll_stop_8996(pll->pll_base); /* stop pll output */ MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0); - /* stop clk */ MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0); + /* stop digital block */ + MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0); + + if (slave) { + /* stop pll output */ + MDSS_PLL_REG_W(pll->pll_base, DSIPHY_PLL_CLKBUFLR_EN, 0); + /* stop clk */ + MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_GLBL_TEST_CTRL, 0); + /* stop digital block */ + MDSS_PLL_REG_W(pll->pll_base, DSIPHY_CMN_CTRL_0, 0x0); + } mdss_pll_resource_enable(pll, false); |