diff options
| author | Aravind Venkateswaran <aravindh@codeaurora.org> | 2016-08-17 11:54:48 -0700 |
|---|---|---|
| committer | Aravind Venkateswaran <aravindh@codeaurora.org> | 2016-08-18 15:02:36 -0700 |
| commit | bd1ead72ec97cae894544ebbb4de8c38355f0732 (patch) | |
| tree | 1d08e4213486d963706e0016e03637eec3c54b65 /drivers/clk | |
| parent | 008f057bbab6dd6629b7e1a3b8c67b650a6b9ef1 (diff) | |
clk: msm: mdss: update DSI PLL programming for msmcobalt
Update the DSI PLL programming for msmcobalt to reflect the
recommended values. The key update is to ensure that the global
bit clock is turned on only after the PLL is locked.
CRs-Fixed: 1033911
Change-Id: I1e4046dd4a7dbb66ad2502e210e58130f08a2b51
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c | 26 |
1 files changed, 24 insertions, 2 deletions
diff --git a/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c b/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c index 1751f49b798c..344613944bad 100644 --- a/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c +++ b/drivers/clk/msm/mdss/mdss-dsi-pll-cobalt.c @@ -345,8 +345,8 @@ static void dsi_pll_disable_pll_bias(struct mdss_pll_resources *rsc) { u32 data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0); - MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data & ~BIT(5)); MDSS_PLL_REG_W(rsc->pll_base, PLL_SYSTEM_MUXES, 0); + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data & ~BIT(5)); ndelay(250); } @@ -359,6 +359,22 @@ static void dsi_pll_enable_pll_bias(struct mdss_pll_resources *rsc) ndelay(250); } +static void dsi_pll_disable_global_clk(struct mdss_pll_resources *rsc) +{ + u32 data; + + data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1); + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data & ~BIT(5))); +} + +static void dsi_pll_enable_global_clk(struct mdss_pll_resources *rsc) +{ + u32 data; + + data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1); + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CLK_CFG1, (data | BIT(5))); +} + static int dsi_pll_enable(struct dsi_pll_vco_clk *vco) { int rc; @@ -385,6 +401,11 @@ static int dsi_pll_enable(struct dsi_pll_vco_clk *vco) } rsc->pll_on = true; + + dsi_pll_enable_global_clk(rsc); + if (rsc->slave) + dsi_pll_enable_global_clk(rsc->slave); + MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0x01); if (rsc->slave) MDSS_PLL_REG_W(rsc->slave->phy_base, PHY_CMN_RBUF_CTRL, 0x01); @@ -395,8 +416,9 @@ error: static void dsi_pll_disable_sub(struct mdss_pll_resources *rsc) { - dsi_pll_disable_pll_bias(rsc); + dsi_pll_disable_global_clk(rsc); MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_RBUF_CTRL, 0); + dsi_pll_disable_pll_bias(rsc); } static void dsi_pll_disable(struct dsi_pll_vco_clk *vco) |