diff options
| author | Deepak Katragadda <dkatraga@codeaurora.org> | 2015-11-12 11:35:01 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-25 16:02:53 -0700 |
| commit | c01c9e3828a1f1e133ff0e1c7856efd59ff20ba7 (patch) | |
| tree | f25714ba4dba6086e5c4075ea48e48f138f72b42 /drivers/clk | |
| parent | 26f78f4bc6f7af7b07072f0f694c6914c9cd8e80 (diff) | |
clk: msm: gdsc: Add support to reset the AON logic for GPU gdsc
On MSMCOBALT, while enabling the gpu_gx_gdsc, the DEMET cells
need to be explicitly reset by using the domain_addr register.
Add support in the gdsc driver to do this.
CRs-Fixed: 922984
Change-Id: I145a581a50719427b7303720a48cd421e2e1ef45
Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/msm/gdsc.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/clk/msm/gdsc.c b/drivers/clk/msm/gdsc.c index aaaa877829e6..e6f31209d835 100644 --- a/drivers/clk/msm/gdsc.c +++ b/drivers/clk/msm/gdsc.c @@ -33,6 +33,7 @@ #define HW_CONTROL_MASK BIT(1) #define SW_COLLAPSE_MASK BIT(0) #define GMEM_CLAMP_IO_MASK BIT(0) +#define GMEM_RESET_MASK BIT(4) #define BCR_BLK_ARES_BIT BIT(0) /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */ @@ -58,6 +59,7 @@ struct gdsc { bool no_status_check_on_disable; bool is_gdsc_enabled; bool allow_clear; + bool reset_aon; void __iomem *domain_addr; void __iomem *hw_ctrl_addr; void __iomem *sw_reset_addr; @@ -167,6 +169,26 @@ static int gdsc_enable(struct regulator_dev *rdev) } if (sc->domain_addr) { + if (sc->reset_aon) { + regval = readl_relaxed(sc->domain_addr); + regval |= GMEM_RESET_MASK; + writel_relaxed(regval, sc->domain_addr); + /* + * Keep reset asserted for at-least 1us before + * continuing. + */ + wmb(); + udelay(1); + + regval &= ~GMEM_RESET_MASK; + writel_relaxed(regval, sc->domain_addr); + /* + * Make sure GMEM_RESET is de-asserted before + * continuing. + */ + wmb(); + } + regval = readl_relaxed(sc->domain_addr); regval &= ~GMEM_CLAMP_IO_MASK; writel_relaxed(regval, sc->domain_addr); @@ -470,6 +492,9 @@ static int gdsc_probe(struct platform_device *pdev) return -ENOMEM; } + sc->reset_aon = of_property_read_bool(pdev->dev.of_node, + "qcom,reset-aon-logic"); + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sw_reset"); if (res) { |