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authorTomasz Figa <t.figa@samsung.com>2013-04-04 13:33:08 +0900
committerKukjin Kim <kgene.kim@samsung.com>2013-04-04 15:51:14 +0900
commitfba79e32a7dfe467a0803a372afa20ccb51ba294 (patch)
treebb4f9b3cf090f2dde5957fd556dc31ebefe776ab /drivers/clk
parenta8b5a39ecbbe5b00554b5025af4464abe12bfcd8 (diff)
clk: exynos4: Export mout_core clock of Exynos4210
This patch enables clock lookup registration for mout_core clock used in Exynos4210 cpufreq driver. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r--drivers/clk/samsung/clk-exynos4.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 5592a78b2edc..f81888dfc5c7 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -311,7 +311,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4),
MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4),
MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
- MUX(none, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
+ MUX_A(mout_core, "mout_core", mout_core_p4210,
+ SRC_CPU, 16, 1, "mout_core"),
MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
SRC_TOP0, 8, 1, "sclk_vpll"),
MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),