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authorSivanesan Rajapupathi <srajap@codeaurora.org>2016-09-07 18:21:55 -0400
committerGerrit - the friendly Code Review server <code-review@localhost>2016-09-14 10:50:12 -0700
commit61ef7e42caaf2b0d1ae312d1abc6f02648e52abb (patch)
tree660f630c5bbf0bb7aa587ed763c4353f3e9c052b /drivers/crypto
parent9b82a4c5896632b62140d1ddda55638fea254007 (diff)
crypto: msm: qce50: DMA-API buffers limitations
Not all memory are DMA'able. See DMA-API-HOWTO.txt. The dummy hash request input buffer is changed to be acquired from coherent memory to kzalloc(). Change-Id: If6961217df08bcf0506eedacb07874dfafd7c1ca CRs-Fixed: 1064055 Acked-by: Che-Min Hsieh <cheminh@qti.qualcomm.com> Signed-off-by: Sivanesan Rajapupathi <srajap@codeaurora.org>
Diffstat (limited to 'drivers/crypto')
-rw-r--r--drivers/crypto/msm/qce50.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/crypto/msm/qce50.c b/drivers/crypto/msm/qce50.c
index 9b42e5ae129a..3562de7fc967 100644
--- a/drivers/crypto/msm/qce50.c
+++ b/drivers/crypto/msm/qce50.c
@@ -94,7 +94,6 @@ enum qce_owner {
struct dummy_request {
struct qce_sha_req sreq;
- uint8_t *in_buf;
struct scatterlist sg;
struct ahash_request areq;
};
@@ -154,6 +153,7 @@ struct qce_device {
atomic_t bunch_cmd_seq;
atomic_t last_intr_seq;
bool cadence_flag;
+ uint8_t *dummyreq_in_buf;
};
static void print_notify_debug(struct sps_event_notify *notify);
@@ -4351,8 +4351,6 @@ static int qce_setup_ce_sps_data(struct qce_device *pce_dev)
(uintptr_t)vaddr;
vaddr += pce_dev->ce_bam_info.ce_burst_size * 2;
}
- pce_dev->dummyreq.in_buf = (uint8_t *)vaddr;
- vaddr += DUMMY_REQ_DATA_LEN;
if ((vaddr - pce_dev->coh_vmem) > pce_dev->memsize ||
iovec_memsize < 0)
panic("qce50: Not enough coherent memory. Allocate %x , need %lx\n",
@@ -5887,8 +5885,8 @@ static int setup_dummy_req(struct qce_device *pce_dev)
"abcdbcdecdefdefgefghfghighijhijkijkljklmklmnlmnomnopnopqopqrpqrs";
int len = DUMMY_REQ_DATA_LEN;
- memcpy(pce_dev->dummyreq.in_buf, input, len);
- sg_set_buf(&pce_dev->dummyreq.sg, pce_dev->dummyreq.in_buf, len);
+ memcpy(pce_dev->dummyreq_in_buf, input, len);
+ sg_set_buf(&pce_dev->dummyreq.sg, pce_dev->dummyreq_in_buf, len);
sg_mark_end(&pce_dev->dummyreq.sg);
pce_dev->dummyreq.sreq.alg = QCE_HASH_SHA1;
@@ -5957,6 +5955,10 @@ void *qce_open(struct platform_device *pdev, int *rc)
if (pce_dev->iovec_vmem == NULL)
goto err_mem;
+ pce_dev->dummyreq_in_buf = kzalloc(DUMMY_REQ_DATA_LEN, GFP_KERNEL);
+ if (pce_dev->dummyreq_in_buf == NULL)
+ goto err_mem;
+
*rc = __qce_init_clk(pce_dev);
if (*rc)
goto err_mem;
@@ -5996,6 +5998,7 @@ err_enable_clk:
__qce_deinit_clk(pce_dev);
err_mem:
+ kfree(pce_dev->dummyreq_in_buf);
kfree(pce_dev->iovec_vmem);
if (pce_dev->coh_vmem)
dma_free_coherent(pce_dev->pdev, pce_dev->memsize,
@@ -6027,6 +6030,7 @@ int qce_close(void *handle)
if (pce_dev->coh_vmem)
dma_free_coherent(pce_dev->pdev, pce_dev->memsize,
pce_dev->coh_vmem, pce_dev->coh_pmem);
+ kfree(pce_dev->dummyreq_in_buf);
kfree(pce_dev->iovec_vmem);
qce_disable_clk(pce_dev);