diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2013-05-14 18:21:17 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-27 19:40:13 -0400 |
| commit | d434e81e59aada1b68444e9a128d56ccc295f66a (patch) | |
| tree | b3ef0c86c6d436afde92cde19814e34e6b813ac8 /drivers/gpu/drm/radeon | |
| parent | 02478a102be592a8b48be03d62f0fdddb51ab786 (diff) | |
drm/radeon/dpm: fix UVD clock setting on cayman
The rv770 version was using the wrong power state type.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon')
| -rw-r--r-- | drivers/gpu/drm/radeon/ni_dpm.c | 40 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/ni_dpm.h | 7 |
2 files changed, 45 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index ae8d3f551e30..5a43cb592666 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -3475,6 +3475,42 @@ static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev, WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE); } +void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, + struct radeon_ps *new_ps, + struct radeon_ps *old_ps) +{ + struct ni_ps *new_state = ni_get_ps(new_ps); + struct ni_ps *current_state = ni_get_ps(old_ps); + + if ((new_ps->vclk == old_ps->vclk) && + (new_ps->dclk == old_ps->dclk)) + return; + + if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >= + current_state->performance_levels[current_state->performance_level_count - 1].sclk) + return; + + radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); +} + +void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, + struct radeon_ps *new_ps, + struct radeon_ps *old_ps) +{ + struct ni_ps *new_state = ni_get_ps(new_ps); + struct ni_ps *current_state = ni_get_ps(old_ps); + + if ((new_ps->vclk == old_ps->vclk) && + (new_ps->dclk == old_ps->dclk)) + return; + + if (new_state->performance_levels[new_state->performance_level_count - 1].sclk < + current_state->performance_levels[current_state->performance_level_count - 1].sclk) + return; + + radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk); +} + void ni_dpm_setup_asic(struct radeon_device *rdev) { struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); @@ -3730,7 +3766,7 @@ int ni_dpm_set_power_state(struct radeon_device *rdev) DRM_ERROR("ni_restrict_performance_levels_before_switch failed\n"); return ret; } - rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); + ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); ret = ni_enable_power_containment(rdev, new_ps, false); if (ret) { DRM_ERROR("ni_enable_power_containment failed\n"); @@ -3780,7 +3816,7 @@ int ni_dpm_set_power_state(struct radeon_device *rdev) DRM_ERROR("rv770_set_sw_state failed\n"); return ret; } - rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); + ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); ret = ni_enable_smc_cac(rdev, new_ps, true); if (ret) { DRM_ERROR("ni_enable_smc_cac failed\n"); diff --git a/drivers/gpu/drm/radeon/ni_dpm.h b/drivers/gpu/drm/radeon/ni_dpm.h index 887442497bff..ac1c7abf2c67 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.h +++ b/drivers/gpu/drm/radeon/ni_dpm.h @@ -238,4 +238,11 @@ void ni_update_current_ps(struct radeon_device *rdev, void ni_update_requested_ps(struct radeon_device *rdev, struct radeon_ps *rps); +void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev, + struct radeon_ps *new_ps, + struct radeon_ps *old_ps); +void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev, + struct radeon_ps *new_ps, + struct radeon_ps *old_ps); + #endif |