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authorVille Syrjälä <ville.syrjala@linux.intel.com>2015-01-19 13:50:47 +0200
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-01-27 09:50:44 +0100
commit160614a2de90f5b36a0fd645d03fada86111fdd3 (patch)
tree15e749b567eb2ccea57846a8cf5badeaba485c49 /drivers/gpu/drm
parent095acd5f8739aa8322820d460e617898baf092df (diff)
drm/i915: Disable RC6 before configuring in on VLV/CHV
Follow the sequence in the BIOS spec and clear the RC_CONTROL register before changing any of the other RC6/RP registers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Deepak S<deepak.s@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b73d601e7226..e7f0f211cca7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4712,6 +4712,9 @@ static void cherryview_enable_rps(struct drm_device *dev)
* hasn't enabled a state yet where we need forcewake, BIOS may have.*/
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+ /* Disable RC states. */
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+
/* 2a: Program RC6 thresholds.*/
I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
@@ -4801,6 +4804,9 @@ static void valleyview_enable_rps(struct drm_device *dev)
/* If VLV, Forcewake all wells, else re-direct to regular path */
gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
+ /* Disable RC states. */
+ I915_WRITE(GEN6_RC_CONTROL, 0);
+
I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
I915_WRITE(GEN6_RP_UP_EI, 66000);