diff options
author | Suman Tatiraju <sumant@codeaurora.org> | 2016-02-11 11:04:48 -0800 |
---|---|---|
committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:20:50 -0700 |
commit | 4457a963d5e00d5f5e290f216dc904ba71596e53 (patch) | |
tree | 578fec502566091b82b3c960c3813ab6e5b3ce09 /drivers/gpu | |
parent | 06308f4fe8a9d5435dfc3e491b0c245df16f0632 (diff) |
msm: kgsl: Specify the initial pwrlevel for each speed bin
Some platforms support multiple GPU clock plans based on the speed
bin in the efuse. Specify the wake up frequency of each speed bin
individually to wake the gpu at the correct powerlevel.
CRs-Fixed: 967494
Change-Id: I9890b8a710d7055c30f9ae7612b092af8fa8a9f5
Signed-off-by: Suman Tatiraju <sumant@codeaurora.org>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/msm/adreno.c | 46 |
1 files changed, 32 insertions, 14 deletions
diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index 0719690df01e..bfd359b0d26b 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -718,10 +718,28 @@ static int adreno_of_parse_pwrlevels(struct adreno_device *adreno_dev, return 0; } + +static void adreno_of_get_initial_pwrlevel(struct adreno_device *adreno_dev, + struct device_node *node) +{ + struct kgsl_device *device = KGSL_DEVICE(adreno_dev); + struct kgsl_pwrctrl *pwr = &device->pwrctrl; + int init_level = 1; + + of_property_read_u32(node, "qcom,initial-pwrlevel", &init_level); + + if (init_level < 0 || init_level > pwr->num_pwrlevels) + init_level = 1; + + pwr->active_pwrlevel = init_level; + pwr->default_pwrlevel = init_level; +} + static int adreno_of_get_legacy_pwrlevels(struct adreno_device *adreno_dev, struct device_node *parent) { struct device_node *node; + int ret; node = of_find_node_by_name(parent, "qcom,gpu-pwrlevels"); @@ -730,7 +748,10 @@ static int adreno_of_get_legacy_pwrlevels(struct adreno_device *adreno_dev, return -EINVAL; } - return adreno_of_parse_pwrlevels(adreno_dev, node); + ret = adreno_of_parse_pwrlevels(adreno_dev, node); + if (ret == 0) + adreno_of_get_initial_pwrlevel(adreno_dev, parent); + return ret; } static int adreno_of_get_pwrlevels(struct adreno_device *adreno_dev, @@ -748,8 +769,15 @@ static int adreno_of_get_pwrlevels(struct adreno_device *adreno_dev, if (of_property_read_u32(child, "qcom,speed-bin", &bin)) continue; - if (bin == adreno_dev->speed_bin) - return adreno_of_parse_pwrlevels(adreno_dev, child); + if (bin == adreno_dev->speed_bin) { + int ret; + + ret = adreno_of_parse_pwrlevels(adreno_dev, child); + if (ret == 0) + adreno_of_get_initial_pwrlevel(adreno_dev, + child); + return ret; + } } return -ENODEV; @@ -775,9 +803,8 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, struct platform_device *pdev) { struct kgsl_device *device = KGSL_DEVICE(adreno_dev); - struct kgsl_pwrctrl *pwr = &device->pwrctrl; struct device_node *node = pdev->dev.of_node; - int i, init_level; + int i; unsigned int timeout; if (of_property_read_string(node, "label", &pdev->name)) { @@ -797,15 +824,6 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, if (adreno_of_get_pwrlevels(adreno_dev, node)) return -EINVAL; - if (of_property_read_u32(node, "qcom,initial-pwrlevel", &init_level)) - init_level = 1; - - if (init_level < 0 || init_level > pwr->num_pwrlevels) - init_level = 1; - - pwr->active_pwrlevel = init_level; - pwr->default_pwrlevel = init_level; - /* get pm-qos-active-latency, set it to default if not found */ if (of_property_read_u32(node, "qcom,pm-qos-active-latency", &device->pwrctrl.pm_qos_active_latency)) |