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authorDave Airlie <airlied@gmail.com>2015-11-07 17:16:59 +1000
committerDave Airlie <airlied@gmail.com>2015-11-07 17:16:59 +1000
commit816d2206f0f9953ca854e4ff1a2749a5cbd62715 (patch)
tree26b8a56c4656a8794911c31246061bfe05d9cd9b /drivers/gpu
parentd0baf9218cacd9dd606c75f9961f94172b16de12 (diff)
parent1b0e3a049efe471c399674fd954500ce97438d30 (diff)
Merge tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/drm-intel into drm-next
Here's a handful of i915 fixes for drm-next/v4.4. Imre's commit alone should address the remaining warnings galore you experienced on Skylake. Almost all of the rest are also fixes against user or QA reported bugs, with references. * tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/drm-intel: drm/i915/skl: disable display side power well support for now drm/i915: Extend DSL readout fix to BDW and SKL. drm/i915: Do graphics device reset under forcewake drm/i915: Skip fence installation for objects with rotated views (v4) drm/i915: add quirk to enable backlight on Dell Chromebook 11 (2015) drm/i915/skl: Prevent unclaimed register writes on skylake. drm/i915: disable CPU PWM also on LPT/SPT backlight disable drm/i915: Fix maxfifo watermark calc on vlv cursor planes drm/i915: add hotplug activation period to hotplug update mask
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c9
-rw-r--r--drivers/gpu/drm/i915/i915_params.c5
-rw-r--r--drivers/gpu/drm/i915/intel_display.c39
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c14
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c7
-rw-r--r--drivers/gpu/drm/i915/intel_runtime_pm.c18
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c11
7 files changed, 79 insertions, 24 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d68328fa175b..0d228f909dcb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -749,7 +749,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
* problem. We may need to extend this to include other platforms,
* but so far testing only shows the problem on HSW.
*/
- if (IS_HASWELL(dev) && !position) {
+ if (HAS_DDI(dev) && !position) {
int i, temp;
for (i = 0; i < 100; i++) {
@@ -4236,9 +4236,10 @@ static void i915_hpd_irq_setup(struct drm_device *dev)
/* Ignore TV since it's buggy */
i915_hotplug_interrupt_update_locked(dev_priv,
- (HOTPLUG_INT_EN_MASK
- | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK),
- hotplug_en);
+ HOTPLUG_INT_EN_MASK |
+ CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
+ CRT_HOTPLUG_ACTIVATION_PERIOD_64,
+ hotplug_en);
}
static irqreturn_t i965_irq_handler(int irq, void *arg)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index ca9b8f644ffe..96bb23865eac 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -38,7 +38,7 @@ struct i915_params i915 __read_mostly = {
.enable_ppgtt = -1,
.enable_psr = 0,
.preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),
- .disable_power_well = 1,
+ .disable_power_well = -1,
.enable_ips = 1,
.prefault_disable = 0,
.load_detect_test = 0,
@@ -127,7 +127,8 @@ MODULE_PARM_DESC(preliminary_hw_support,
module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0600);
MODULE_PARM_DESC(disable_power_well,
- "Disable the power well when possible (default: true)");
+ "Disable display power wells when possible "
+ "(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)");
module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600);
MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 82128b95785c..6795df562341 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2389,22 +2389,24 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
* framebuffer compression. For simplicity, we always install
* a fence as the cost is not that onerous.
*/
- ret = i915_gem_object_get_fence(obj);
- if (ret == -EDEADLK) {
- /*
- * -EDEADLK means there are no free fences
- * no pending flips.
- *
- * This is propagated to atomic, but it uses
- * -EDEADLK to force a locking recovery, so
- * change the returned error to -EBUSY.
- */
- ret = -EBUSY;
- goto err_unpin;
- } else if (ret)
- goto err_unpin;
+ if (view.type == I915_GGTT_VIEW_NORMAL) {
+ ret = i915_gem_object_get_fence(obj);
+ if (ret == -EDEADLK) {
+ /*
+ * -EDEADLK means there are no free fences
+ * no pending flips.
+ *
+ * This is propagated to atomic, but it uses
+ * -EDEADLK to force a locking recovery, so
+ * change the returned error to -EBUSY.
+ */
+ ret = -EBUSY;
+ goto err_unpin;
+ } else if (ret)
+ goto err_unpin;
- i915_gem_object_pin_fence(obj);
+ i915_gem_object_pin_fence(obj);
+ }
dev_priv->mm.interruptible = true;
intel_runtime_pm_put(dev_priv);
@@ -2430,7 +2432,9 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
WARN_ONCE(ret, "Couldn't get view from plane state!");
- i915_gem_object_unpin_fence(obj);
+ if (view.type == I915_GGTT_VIEW_NORMAL)
+ i915_gem_object_unpin_fence(obj);
+
i915_gem_object_unpin_from_display_plane(obj, &view);
}
@@ -14695,6 +14699,9 @@ static struct intel_quirk intel_quirks[] = {
/* Dell Chromebook 11 */
{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
+
+ /* Dell Chromebook 11 (2015 version) */
+ { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
};
static void intel_init_quirks(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index b05c6d9b3be7..a24df35e11e7 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -732,6 +732,20 @@ static void lpt_disable_backlight(struct intel_connector *connector)
intel_panel_actually_set_backlight(connector, 0);
+ /*
+ * Although we don't support or enable CPU PWM with LPT/SPT based
+ * systems, it may have been enabled prior to loading the
+ * driver. Disable to avoid warnings on LCPLL disable.
+ *
+ * This needs rework if we need to add support for CPU PWM on PCH split
+ * platforms.
+ */
+ tmp = I915_READ(BLC_PWM_CPU_CTL2);
+ if (tmp & BLM_PWM_ENABLE) {
+ DRM_DEBUG_KMS("cpu backlight was enabled, disabling\n");
+ I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
+ }
+
tmp = I915_READ(BLC_PWM_PCH_CTL1);
I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9dda3eaebd12..d52a15df6917 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1135,7 +1135,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
case DRM_PLANE_TYPE_CURSOR:
for (level = 0; level < wm_state->num_levels; level++)
wm_state->sr[level].cursor =
- wm_state->sr[level].cursor;
+ wm_state->wm[level].cursor;
break;
case DRM_PLANE_TYPE_PRIMARY:
for (level = 0; level < wm_state->num_levels; level++)
@@ -2818,7 +2818,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
int plane;
u32 val;
+ memset(ddb, 0, sizeof(*ddb));
+
for_each_pipe(dev_priv, pipe) {
+ if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
+ continue;
+
for_each_plane(dev_priv, pipe, plane) {
val = I915_READ(PLANE_BUF_CFG(pipe, plane));
skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ec010ee74050..d89c1d0aa1b7 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1811,6 +1811,21 @@ static struct i915_power_well bxt_power_wells[] = {
}
};
+static int
+sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
+ int disable_power_well)
+{
+ if (disable_power_well >= 0)
+ return !!disable_power_well;
+
+ if (IS_SKYLAKE(dev_priv)) {
+ DRM_DEBUG_KMS("Disabling display power well support\n");
+ return 0;
+ }
+
+ return 1;
+}
+
#define set_power_wells(power_domains, __power_wells) ({ \
(power_domains)->power_wells = (__power_wells); \
(power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
@@ -1827,6 +1842,9 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
+ i915.disable_power_well);
+
mutex_init(&power_domains->lock);
/*
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 1663ea55e37c..43cba129a0c0 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1531,13 +1531,22 @@ static int (*intel_get_gpu_reset(struct drm_device *dev))(struct drm_device *)
int intel_gpu_reset(struct drm_device *dev)
{
+ struct drm_i915_private *dev_priv = to_i915(dev);
int (*reset)(struct drm_device *);
+ int ret;
reset = intel_get_gpu_reset(dev);
if (reset == NULL)
return -ENODEV;
- return reset(dev);
+ /* If the power well sleeps during the reset, the reset
+ * request may be dropped and never completes (causing -EIO).
+ */
+ intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
+ ret = reset(dev);
+ intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+
+ return ret;
}
bool intel_has_gpu_reset(struct drm_device *dev)