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authorMichel Dänzer <michel.daenzer@amd.com>2013-09-18 15:39:41 +0200
committerAlex Deucher <alexander.deucher@amd.com>2013-09-20 17:32:58 -0400
commita537314e0b539e22934d3cffeb0b1f476e56491c (patch)
treec344b6d4416d0a891d2f0defa5a6c33dde93956f /drivers/gpu
parent328a50c7b09d313ab9278f972950da414d348eb1 (diff)
drm/radeon/cik: Fix encoding of number of banks in tiling configuration info
There are multiple valid values, not just 0 or 1. Required to properly support 2D tiling in the userspace drivers. Cc: stable@vger.kernel.org Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/radeon/cik.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index c0714d72610b..5e6802d8a59a 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2845,10 +2845,8 @@ static void cik_gpu_init(struct radeon_device *rdev)
rdev->config.cik.tile_config |= (3 << 0);
break;
}
- if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
- rdev->config.cik.tile_config |= 1 << 4;
- else
- rdev->config.cik.tile_config |= 0 << 4;
+ rdev->config.cik.tile_config |=
+ ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
rdev->config.cik.tile_config |=
((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
rdev->config.cik.tile_config |=