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authorJosh Wu <josh.wu@atmel.com>2013-08-27 12:28:00 +0100
committerJonathan Cameron <jic23@kernel.org>2013-09-18 19:43:20 +0100
commitdb10e201172f48dad29d81ee1fec96384f0eab35 (patch)
tree8d99b9b0c2db7151988ba3f5c961763587e558a2 /drivers/iio/adc
parentc3cb718acc17f8e0d6b4b8d1f8ca9a20d1999159 (diff)
iio: at91: fix adc_clk overflow
The adc_clk variable is currently defined using a 32-bits unsigned integer, which will overflow under some very valid range of operations. Such overflow will occur if, for example, the parent clock is set to a 20MHz frequency and the ADC startup time is larger than 215ns. To fix this, introduce an intermediate variable holding the clock rate in kHz. Signed-off-by: Josh Wu <josh.wu@atmel.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jonathan Cameron <jic23@kernel.org>
Diffstat (limited to 'drivers/iio/adc')
-rw-r--r--drivers/iio/adc/at91_adc.c11
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/iio/adc/at91_adc.c b/drivers/iio/adc/at91_adc.c
index 84be63bdf038..0f16b553e063 100644
--- a/drivers/iio/adc/at91_adc.c
+++ b/drivers/iio/adc/at91_adc.c
@@ -556,7 +556,7 @@ static const struct iio_info at91_adc_info = {
static int at91_adc_probe(struct platform_device *pdev)
{
- unsigned int prsc, mstrclk, ticks, adc_clk, shtim;
+ unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
int ret;
struct iio_dev *idev;
struct at91_adc_state *st;
@@ -649,6 +649,7 @@ static int at91_adc_probe(struct platform_device *pdev)
*/
mstrclk = clk_get_rate(st->clk);
adc_clk = clk_get_rate(st->adc_clk);
+ adc_clk_khz = adc_clk / 1000;
prsc = (mstrclk / (2 * adc_clk)) - 1;
if (!st->startup_time) {
@@ -662,15 +663,15 @@ static int at91_adc_probe(struct platform_device *pdev)
* defined in the electrical characteristics of the board, divided by 8.
* The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock
*/
- ticks = round_up((st->startup_time * adc_clk /
- 1000000) - 1, 8) / 8;
+ ticks = round_up((st->startup_time * adc_clk_khz /
+ 1000) - 1, 8) / 8;
/*
* a minimal Sample and Hold Time is necessary for the ADC to guarantee
* the best converted final value between two channels selection
* The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
*/
- shtim = round_up((st->sample_hold_time * adc_clk /
- 1000000) - 1, 1);
+ shtim = round_up((st->sample_hold_time * adc_clk_khz /
+ 1000) - 1, 1);
reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;