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authorRobin Murphy <Robin.Murphy@arm.com>2015-07-29 19:46:10 +0100
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-22 11:15:21 -0700
commit65affae5ca43eb7b893acd511d69390fea64bd34 (patch)
treef265f7904aa74dee884571cb5facb12284c89f9a /drivers/iommu
parent2024cabb4ddb0e3f5f6312e20de743ce7fdaa746 (diff)
iommu/arm-smmu: Remove arm_smmu_flush_pgtable()
With the io-pgtable code now enforcing its own appropriate sync points, the vestigial flush_pgtable callback becomes entirely redundant, so remove it altogether. Change-Id: I0c5c2dfabb873e6045f0919ec853dd825f560564 Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> [pdaly@codeaurora.org Resolve minor conflicts]
Diffstat (limited to 'drivers/iommu')
-rw-r--r--drivers/iommu/arm-smmu.c17
1 files changed, 0 insertions, 17 deletions
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index acd2e3bee86b..5f100941465f 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -985,22 +985,6 @@ static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
arm_smmu_disable_clocks_atomic(smmu);
}
-static void arm_smmu_flush_pgtable(void *addr, size_t size, void *cookie)
-{
- struct arm_smmu_domain *smmu_domain = cookie;
- int coherent_htw_disable = smmu_domain->attributes &
- (1 << DOMAIN_ATTR_COHERENT_HTW_DISABLE);
-
-
- /*
- * Ensure new page tables are visible to a coherent hardware walker.
- * The page table code deals with flushing for the non-coherent case.
- */
- if (!coherent_htw_disable &&
- smmu_domain->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
- dsb(ishst);
-}
-
struct arm_smmu_secure_pool_chunk {
void *addr;
size_t size;
@@ -1090,7 +1074,6 @@ static struct iommu_gather_ops arm_smmu_gather_ops = {
.tlb_flush_all = arm_smmu_tlb_inv_context,
.tlb_add_flush = arm_smmu_tlb_inv_range_nosync,
.tlb_sync = arm_smmu_tlb_sync,
- .flush_pgtable = arm_smmu_flush_pgtable,
.alloc_pages_exact = arm_smmu_alloc_pages_exact,
.free_pages_exact = arm_smmu_free_pages_exact,
};