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authorTanvi Aggarwal <tanvia@codeaurora.org>2017-05-17 11:54:48 +0530
committerGerrit - the friendly Code Review server <code-review@localhost>2017-05-23 00:53:36 -0700
commit7717905408bfdcb59aec06fad7f49a51d93530c9 (patch)
treec93ce6043ed237a8308094011251749a0e55b89e /drivers/media
parent60be71604a84d2e047215cb702d6324379a353bb (diff)
msm: camera: sensor: Change REFGEN for DPHY CLK/DATA to internal bias
Changing REFGEN for DPHY CLK/DATA to internal bias as suggested by hardware team for a rarely seen line noise issue on msm8998 platform. CRs-Fixed: 2037215 Change-Id: I37a40db8b3d2abba934c049f8ab49e0b977877f2 Signed-off-by: Tanvi Aggarwal <tanvia@codeaurora.org>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_1_hwreg.h2
-rw-r--r--drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_hwreg.h2
-rw-r--r--drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c18
-rw-r--r--drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h2
4 files changed, 22 insertions, 2 deletions
diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_1_hwreg.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_1_hwreg.h
index 9120a4cc85ca..5dbcbd219732 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_1_hwreg.h
+++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_1_hwreg.h
@@ -100,6 +100,8 @@ struct csiphy_reg_3ph_parms_t csiphy_v5_0_1_3ph = {
{0x38, 0xFE},
{0x81c, 0x2},
{0x700, 0x80},
+ {0x724, 0x04},
+ {0x024, 0x04},
};
struct csiphy_settings_t csiphy_combo_mode_v5_0_1 = {
diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_hwreg.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_hwreg.h
index 8591f0646080..98d0b933bba2 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_hwreg.h
+++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_5_0_hwreg.h
@@ -101,6 +101,8 @@ struct csiphy_reg_3ph_parms_t csiphy_v5_0_3ph = {
{0x38, 0xFE},
{0x81c, 0x6},
{0x700, 0x80},
+ {0x724, 0x04},
+ {0x024, 0x04},
};
struct csiphy_settings_t csiphy_combo_mode_v5_0 = {
diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
index 214dd6f3406d..8d091320cbca 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
@@ -684,14 +684,20 @@ static int msm_csiphy_2phase_lane_config_v50(
csiphybase + csiphy_dev->ctrl_reg->
csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl15.addr + offset);
- if (mask == CLOCK_LANE)
+ if (mask == CLOCK_LANE) {
msm_camera_io_w(csiphy_dev->ctrl_reg->
csiphy_3ph_reg.
mipi_csiphy_2ph_lnck_ctrl0.data,
csiphybase + csiphy_dev->ctrl_reg->
csiphy_3ph_reg.
mipi_csiphy_2ph_lnck_ctrl0.addr);
- else
+ msm_camera_io_w(csiphy_dev->ctrl_reg->
+ csiphy_3ph_reg.
+ mipi_csiphy_2ph_lnck_ctrl9.data,
+ csiphybase + csiphy_dev->ctrl_reg->
+ csiphy_3ph_reg.
+ mipi_csiphy_2ph_lnck_ctrl9.addr);
+ } else {
msm_camera_io_w(csiphy_dev->ctrl_reg->
csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl0.data,
@@ -699,6 +705,14 @@ static int msm_csiphy_2phase_lane_config_v50(
csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_ctrl0.addr +
offset);
+ msm_camera_io_w(csiphy_dev->ctrl_reg->
+ csiphy_3ph_reg.
+ mipi_csiphy_2ph_lnn_ctrl9.data,
+ csiphybase + csiphy_dev->ctrl_reg->
+ csiphy_3ph_reg.
+ mipi_csiphy_2ph_lnn_ctrl9.addr +
+ offset);
+ }
msm_camera_io_w(csiphy_dev->ctrl_reg->
csiphy_3ph_reg.
mipi_csiphy_2ph_lnn_cfg1.data,
diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h
index c1a9748e8af5..c33f183963cc 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h
+++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h
@@ -142,6 +142,8 @@ struct csiphy_reg_3ph_parms_t {
struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl14;
struct csiphy_reg_t mipi_csiphy_3ph_cmn_ctrl7_cphy;
struct csiphy_reg_t mipi_csiphy_2ph_lnck_ctrl0;
+ struct csiphy_reg_t mipi_csiphy_2ph_lnck_ctrl9;
+ struct csiphy_reg_t mipi_csiphy_2ph_lnn_ctrl9;
};
struct csiphy_ctrl_t {