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| author | Sahitya Tummala <stummala@codeaurora.org> | 2013-06-10 16:32:51 +0530 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-27 10:28:42 -0700 |
| commit | a467484ee963486ba9b527c6ca2dafd0f3b34eda (patch) | |
| tree | 594febf80ea801744da82fd8233b5da4703960f9 /drivers/mmc/host/s3cmci.c | |
| parent | b2f263c3ea2f0dd31343b10b6df5b46f0cddb7f4 (diff) | |
mmc: sdhci-msm: calculate timeout value based on the base clock
The driver currently uses fixed timeout value from capabilities
register (bit 5-0) to calculate the timeout which is advertized
as 50MHz. But the driver uses SDHCI_QUIRK2_ALWAYS_USE_BASE_CLOCK
and controls the base clock (MCLK) directly. So during card
initialization, the frequency would be 400KHz but still timeout
is calculated at 50MHz which is wrong. This patch fixes this by
using the current base clock frequency to calculate the timeout.
The controller internally multiplies the timeout control register
value by 4 with the assumption that driver always uses fixed
timeout clock value from capabilities register. Add a quirk
SDHCI_QUIRK2_DIVIDE_TOUT_BY_4 to avoid this multiplicaiton in
case base clock is used for timeout calculation.
CRs-fixed: 498159
Change-Id: I503fd16132bf17e590239997d6970b9b730d4202
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
[subhashj@codeaurora.org: fixed minor merge conflict]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Diffstat (limited to 'drivers/mmc/host/s3cmci.c')
0 files changed, 0 insertions, 0 deletions