diff options
| author | Sahitya Tummala <stummala@codeaurora.org> | 2013-04-25 11:50:56 +0530 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-27 10:28:38 -0700 |
| commit | f957bdbd793ed262bf43a2a3059ff75f17b89c83 (patch) | |
| tree | 46d1850320b8de8555ea69702076e83f7ffdcb93 /drivers/mmc/host | |
| parent | 2f5949b9d2b8a852870c4b26ff84224d75fb46ad (diff) | |
mmc: sdhci-msm: wait for SW reset to be complete
Wait for SW reset to be complete before proceeding further
in probe. Otherwise, any register writes immediately
after the reset would be ignored/reset.
Change-Id: If1c7f5debfca6f45a0fdb08bc759ad04b96fd86c
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Diffstat (limited to 'drivers/mmc/host')
| -rw-r--r-- | drivers/mmc/host/sdhci-msm.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4c8631d5e3dc..ea8614707ca5 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2050,6 +2050,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) struct resource *core_memres = NULL; int ret = 0, pwr_irq = 0, dead = 0; u16 host_version; + u32 pwr; pr_debug("%s: Enter %s\n", dev_name(&pdev->dev), __func__); msm_host = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_msm_host), @@ -2158,7 +2159,21 @@ static int sdhci_msm_probe(struct platform_device *pdev) } /* Set SW_RST bit in POWER register (Offset 0x0) */ - writel_relaxed(CORE_SW_RST, msm_host->core_mem + CORE_POWER); + writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) | + CORE_SW_RST, msm_host->core_mem + CORE_POWER); + /* + * SW reset can take upto 10HCLK + 15MCLK cycles. + * Calculating based on min clk rates (hclk = 27MHz, + * mclk = 400KHz) it comes to ~40us. Let's poll for + * max. 1ms for reset completion. + */ + ret = readl_poll_timeout(msm_host->core_mem + CORE_POWER, + pwr, !(pwr & CORE_SW_RST), 100, 10); + + if (ret) { + dev_err(&pdev->dev, "reset failed (%d)\n", ret); + goto vreg_deinit; + } /* Set HC_MODE_EN bit in HC_MODE register */ writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE)); |