diff options
| author | Sahitya Tummala <stummala@codeaurora.org> | 2013-08-29 16:21:08 +0530 |
|---|---|---|
| committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-27 10:28:53 -0700 |
| commit | 2ba264341c60b4a5ab95ef75575a92b941cedc9d (patch) | |
| tree | 9af8fc7e7197febcfc4285a9adeb050d23336f8e /drivers/mmc | |
| parent | 3118da1c322234006a43f84aef70a399ac3ce643 (diff) | |
mmc: sdhci-msm: Fix issue with power save bit enablement
The power save bit is currently enabled based on the clock
rate (clk_rate > 400KHz) within struct sdhci_msm_host. But this
clk_rate is updated with the latest value down in this function
sdhci_msm_set_clock(). So during runtime/system resume when the
card is still in initialization phase, the power save bit is
getting enabled when sdhci_msm_set_clock() is called for the
first time based on the previous rate which is wrong.
Change-Id: I05dc8a4a760f658935de3831aaf8dd3b2b996466
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/host/sdhci-msm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index a25f3e83037c..7bdc85437854 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2405,7 +2405,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) curr_pwrsave = !!(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) & CORE_CLK_PWRSAVE); - if ((msm_host->clk_rate > 400000) && + if ((clock > 400000) && !curr_pwrsave && mmc_host_may_gate_card(host->mmc->card)) writel_relaxed(readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC) | CORE_CLK_PWRSAVE, |