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authorMarc Kleine-Budde <mkl@pengutronix.de>2015-05-08 15:22:36 +0200
committerMarc Kleine-Budde <mkl@pengutronix.de>2015-09-21 08:38:22 +0200
commitf377bff0235708ded5f94e581855d6bd678cd2d1 (patch)
tree774cda8108112b637350f922a6911581d03d84dc /drivers/net/can
parent749de6fce2dd67b40f4118bf694be37f9093c3f5 (diff)
can: flexcan: rename feature into quirks
This patch renames the "features" member of struct flexcan_devtype_data to "quirks". The corresponding defines are renamed too, to reflect what they actually do. FLEXCAN_HAS_V10_FEATURES -> FLEXCAN_QUIRK_DISABLE_RXFG FLEXCAN_HAS_BROKEN_ERR_STATE -> FLEXCAN_QUIRK_BROKEN_ERR_STATE FLEXCAN_HAS_MECR_FEATURES -> FLEXCAN_QUIRK_DISABLE_MECR Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Diffstat (limited to 'drivers/net/can')
-rw-r--r--drivers/net/can/flexcan.c20
1 files changed, 10 insertions, 10 deletions
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 70cdbfcebb46..dd5a9353e0c5 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -187,9 +187,9 @@
*
* Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
*/
-#define FLEXCAN_HAS_V10_FEATURES BIT(1) /* For core version >= 10 */
-#define FLEXCAN_HAS_BROKEN_ERR_STATE BIT(2) /* [TR]WRN_INT not connected */
-#define FLEXCAN_HAS_MECR_FEATURES BIT(3) /* Memory error detection */
+#define FLEXCAN_QUIRK_BROKEN_ERR_STATE BIT(1) /* [TR]WRN_INT not connected */
+#define FLEXCAN_QUIRK_DISABLE_RXFG BIT(2) /* Disable RX FIFO Global mask */
+#define FLEXCAN_QUIRK_DISABLE_MECR BIT(3) /* Disble Memory error detection */
/* Structure of the message buffer */
struct flexcan_mb {
@@ -244,7 +244,7 @@ struct flexcan_regs {
};
struct flexcan_devtype_data {
- u32 features; /* hardware controller features */
+ u32 quirks; /* quirks needed for different IP cores */
};
struct flexcan_priv {
@@ -263,17 +263,17 @@ struct flexcan_priv {
};
static struct flexcan_devtype_data fsl_p1010_devtype_data = {
- .features = FLEXCAN_HAS_BROKEN_ERR_STATE,
+ .quirks = FLEXCAN_QUIRK_BROKEN_ERR_STATE,
};
static struct flexcan_devtype_data fsl_imx28_devtype_data;
static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
- .features = FLEXCAN_HAS_V10_FEATURES,
+ .quirks = FLEXCAN_QUIRK_DISABLE_RXFG,
};
static struct flexcan_devtype_data fsl_vf610_devtype_data = {
- .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
+ .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_DISABLE_MECR,
};
static const struct can_bittiming_const flexcan_bittiming_const = {
@@ -870,7 +870,7 @@ static int flexcan_chip_start(struct net_device *dev)
* on most Flexcan cores, too. Otherwise we don't get
* any error warning or passive interrupts.
*/
- if (priv->devtype_data->features & FLEXCAN_HAS_BROKEN_ERR_STATE ||
+ if (priv->devtype_data->quirks & FLEXCAN_QUIRK_BROKEN_ERR_STATE ||
priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
reg_ctrl |= FLEXCAN_CTRL_ERR_MSK;
else
@@ -900,7 +900,7 @@ static int flexcan_chip_start(struct net_device *dev)
flexcan_write(0x0, &regs->rx14mask);
flexcan_write(0x0, &regs->rx15mask);
- if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
+ if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_RXFG)
flexcan_write(0x0, &regs->rxfgmask);
/* On Vybrid, disable memory error detection interrupts
@@ -909,7 +909,7 @@ static int flexcan_chip_start(struct net_device *dev)
* false positive memory errors and put the device in
* freeze mode.
*/
- if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) {
+ if (priv->devtype_data->quirks & FLEXCAN_QUIRK_DISABLE_MECR) {
/* Follow the protocol as described in "Detection
* and Correction of Memory Errors" to write to
* MECR register