diff options
| author | Tony Truong <truong@codeaurora.org> | 2015-12-22 14:14:23 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 21:16:41 -0700 |
| commit | dac841cd75a9d123fc0471237a038a697410b007 (patch) | |
| tree | 87c426ace6a8bdd1d61c461cf10dbf922fea0805 /drivers/pci/host | |
| parent | 37311842a099aee8164f39d9bf438f411d10aa78 (diff) | |
msm: pcie: add support to modify the Cpl timeout for RC
Add support to modify the completion timeout range for
the root complex. This value/range will inform when
the root complex should send out a completion if the
endpoint does not respond.
Change-Id: Iabca3f637d9abf6c93810c84d81ff6b5c77d4528
Signed-off-by: Tony Truong <truong@codeaurora.org>
Diffstat (limited to 'drivers/pci/host')
| -rw-r--r-- | drivers/pci/host/pci-msm.c | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 575d2fca54a9..02a32935ce1f 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -569,6 +569,7 @@ struct msm_pcie_dev_t { bool ext_ref_clk; bool common_phy; uint32_t ep_latency; + uint32_t cpl_timeout; uint32_t current_bdf; short current_short_bdf; uint32_t tlp_rd_size; @@ -1778,6 +1779,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) dev->common_phy); PCIE_DBG_FS(dev, "ep_latency: %dms\n", dev->ep_latency); + PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n", + dev->cpl_timeout); PCIE_DBG_FS(dev, "current_bdf: 0x%x\n", dev->current_bdf); PCIE_DBG_FS(dev, "tlp_rd_size: 0x%x\n", @@ -3343,6 +3346,12 @@ static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev) else msm_pcie_write_reg(dev->dm_core, PCIE20_AUX_CLK_FREQ_REG, 0x01); + /* configure the completion timeout value for PCIe core */ + if (dev->cpl_timeout && dev->bridge_found) + msm_pcie_write_reg_field(dev->dm_core, + PCIE20_DEVICE_CONTROL2_STATUS2, + 0xf, dev->cpl_timeout); + /* Enable AER on RC */ msm_pcie_write_mask(dev->dm_core + PCIE20_BRIDGE_CTRL, 0, BIT(16)|BIT(17)); @@ -4480,6 +4489,11 @@ int msm_pcie_enumerate(u32 rc_idx) msm_pcie_write_mask(dev->dm_core + PCIE20_COMMAND_STATUS, 0, BIT(2)|BIT(1)); + if (dev->cpl_timeout && dev->bridge_found) + msm_pcie_write_reg_field(dev->dm_core, + PCIE20_DEVICE_CONTROL2_STATUS2, + 0xf, dev->cpl_timeout); + if (dev->shadow_en) { u32 val = readl_relaxed(dev->dm_core + PCIE20_COMMAND_STATUS); @@ -5516,6 +5530,18 @@ static int msm_pcie_probe(struct platform_device *pdev) PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: ep-latency: 0x%x.\n", rc_idx, msm_pcie_dev[rc_idx].ep_latency); + msm_pcie_dev[rc_idx].cpl_timeout = 0; + ret = of_property_read_u32((&pdev->dev)->of_node, + "qcom,cpl-timeout", + &msm_pcie_dev[rc_idx].cpl_timeout); + if (ret) + PCIE_DBG(&msm_pcie_dev[rc_idx], + "RC%d: Using default cpl-timeout.\n", + rc_idx); + else + PCIE_DBG(&msm_pcie_dev[rc_idx], "RC%d: cpl-timeout: 0x%x.\n", + rc_idx, msm_pcie_dev[rc_idx].cpl_timeout); + msm_pcie_dev[rc_idx].tlp_rd_size = PCIE_TLP_RD_SIZE; ret = of_property_read_u32(pdev->dev.of_node, "qcom,tlp-rd-size", |