diff options
| author | Tony Truong <truong@codeaurora.org> | 2016-05-09 16:36:50 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-16 20:10:18 -0700 |
| commit | 6689a316575c9a9df456eb3c9b97a37304e2bff4 (patch) | |
| tree | b436475eef7400010d9c29889b2d6e3da4866403 /drivers/pci | |
| parent | 5834faf08567295e2af94003347a3aeae7c984ef (diff) | |
msm: pcie: update PCIe PHY registers and sequences for msmcobalt
PCIe PHY on msmcobalt has different register offsets and does not
support the same PHY sequences as other platforms. Thus, update
the PHY register offsets and sequences for msmcobalt.
Change-Id: If87bd507228476fee9713f88c06a1cf04b13f163
Signed-off-by: Tony Truong <truong@codeaurora.org>
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/host/pci-msm.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 21cc701aa5e3..6a07ba2c638f 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -57,6 +57,13 @@ #define RX_BASE 0x400 #define PCS_BASE 0x800 #define PCS_MISC_BASE 0x600 + +#elif defined(CONFIG_ARCH_MSMCOBALT) +#define TX_BASE 0 +#define RX_BASE 0 +#define PCS_BASE 0x800 +#define PCS_MISC_BASE 0 + #else #define PCIE_VENDOR_ID_RCP 0x17cb #define PCIE_DEVICE_ID_RCP 0x0104 @@ -1022,6 +1029,12 @@ static void pcie_phy_dump(struct msm_pcie_dev_t *dev) int i, size; u32 write_val; + if (dev->phy_ver >= 0x20) { + PCIE_DUMP(dev, "PCIe: RC%d PHY dump is not supported\n", + dev->rc_idx); + return; + } + PCIE_DUMP(dev, "PCIe: RC%d PHY testbus\n", dev->rc_idx); pcie_phy_dump_test_cntrl(dev, 0x18, 0x19, 0x1A, 0x1B); @@ -1502,6 +1515,9 @@ static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev) { u8 common_phy; + if (dev->phy_ver >= 0x20) + return; + PCIE_DBG(dev, "RC%d: Initializing PCIe PHY Port\n", dev->rc_idx); if (dev->common_phy) @@ -1597,6 +1613,15 @@ static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev) static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev) { + if (dev->phy_ver >= 0x20) { + if (readl_relaxed(dev->phy + + PCIE_N_PCS_STATUS(dev->rc_idx, dev->common_phy)) & + BIT(6)) + return false; + else + return true; + } + if (!(readl_relaxed(dev->phy + PCIE_COM_PCS_READY_STATUS) & 0x1)) return false; else |