scsi: ufs-qcom: change device reference clock control

As of HW major version 2, bit 'UFS_DEV_REF_CLK_EN' which is used to
gate/ungate the ref_clk to external UFS device, was moved into the
UFS register space to UFS_CFG1 register. This change adds support
to appropriately control the device reference clock and it also
adds the missing documentation for the device reference clock control
register address space.

Change-Id: I66a6a75dc5a1cf130b1cee90ae20f9f950edfb3a
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
[subhashj@codeaurora.org: resolved trivial merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>

1 files changed, 31 insertions, 29 deletions

diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index 69077678a198..f3e2fde8b4c0 100644
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -801,17 +801,16 @@ static int ufs_qcom_update_bus_bw_vote(struct ufs_qcom_host *host)
 	return err;
 }
 
-#define UFS_REF_CLK_EN	(1 << 5)
-static void ufs_qcom_enable_dev_ref_clk(struct ufs_qcom_host *host, bool enable)
+static void ufs_qcom_dev_ref_clk_ctrl(struct ufs_qcom_host *host, bool enable)
 {
 	if (host->dev_ref_clk_ctrl_mmio &&
 	    (enable ^ host->is_dev_ref_clk_enabled)) {
 		u32 temp = readl_relaxed(host->dev_ref_clk_ctrl_mmio);
 
 		if (enable)
-			temp |= UFS_REF_CLK_EN;
+			temp |= host->dev_ref_clk_en_mask;
 		else
-			temp &= ~UFS_REF_CLK_EN;
+			temp &= ~host->dev_ref_clk_en_mask;
 
 		/*
 		 * If we are here to disable this clock it might be immediately
@@ -885,7 +884,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 		/* enable the device ref clock before changing to HS mode */
 		if (!ufshcd_is_hs_mode(&hba->pwr_info) &&
 			ufshcd_is_hs_mode(dev_req_params))
-			ufs_qcom_enable_dev_ref_clk(host, true);
+			ufs_qcom_dev_ref_clk_ctrl(host, true);
 		break;
 	case POST_CHANGE:
 		if (ufs_qcom_cfg_timers(hba, dev_req_params->gear_rx,
@@ -917,7 +916,7 @@ static int ufs_qcom_pwr_change_notify(struct ufs_hba *hba,
 		/* disable the device ref clock if entered PWM mode */
 		if (ufshcd_is_hs_mode(&hba->pwr_info) &&
 			!ufshcd_is_hs_mode(dev_req_params))
-			ufs_qcom_enable_dev_ref_clk(host, false);
+			ufs_qcom_dev_ref_clk_ctrl(host, false);
 		break;
 	default:
 		ret = -EINVAL;
@@ -1075,7 +1074,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on)
 		}
 		/* enable the device ref clock for HS mode*/
 		if (ufshcd_is_hs_mode(&hba->pwr_info))
-			ufs_qcom_enable_dev_ref_clk(host, true);
+			ufs_qcom_dev_ref_clk_ctrl(host, true);
 		vote = host->bus_vote.saved_vote;
 		if (vote == host->bus_vote.min_bw_vote)
 			ufs_qcom_update_bus_bw_vote(host);
@@ -1086,7 +1085,7 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on)
 			/* turn off UFS local PHY ref_clk */
 			ufs_qcom_phy_disable_ref_clk(host->generic_phy);
 			/* disable device ref_clk */
-			ufs_qcom_enable_dev_ref_clk(host, false);
+			ufs_qcom_dev_ref_clk_ctrl(host, false);
 		}
 		vote = host->bus_vote.min_bw_vote;
 	}
@@ -1196,8 +1195,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
 	struct device *dev = hba->dev;
 	struct platform_device *pdev = to_platform_device(dev);
 	struct ufs_qcom_host *host;
-	u8 major;
-	u16 minor, step;
 	struct resource *res;
 
 	if (strlen(android_boot_dev) && strcmp(android_boot_dev, dev_name(dev)))
@@ -1252,10 +1249,32 @@ static int ufs_qcom_init(struct ufs_hba *hba)
 	if (err)
 		goto out_host_free;
 
-	ufs_qcom_get_controller_revision(hba, &major, &minor, &step);
+	ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
+		&host->hw_ver.minor, &host->hw_ver.step);
+
+	/* "dev_ref_clk_ctrl_mem" is optional resource */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (!res) {
+		dev_info(dev, "%s: dev_ref_clk_ctrl_mem resource not found\n",
+			__func__);
+	} else {
+		host->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res);
+		if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
+			dev_warn(dev,
+				"%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
+				__func__, PTR_ERR(host->dev_ref_clk_ctrl_mmio));
+			host->dev_ref_clk_ctrl_mmio = NULL;
+		}
+		/* Set the correct mask for the device ref. clock enable bit */
+		if (host->hw_ver.major >= 0x02)
+			host->dev_ref_clk_en_mask = BIT(26);
+		else
+			host->dev_ref_clk_en_mask = BIT(5);
+	}
+
 	/* update phy revision information before calling phy_init() */
 	ufs_qcom_phy_save_controller_version(host->generic_phy,
-					     major, minor, step);
+		host->hw_ver.major, host->hw_ver.minor, host->hw_ver.step);
 
 	phy_init(host->generic_phy);
 	err = phy_power_on(host->generic_phy);
@@ -1267,8 +1286,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
 		goto out_disable_phy;
 
 	ufs_qcom_set_caps(hba);
-	ufs_qcom_get_controller_revision(hba, &host->hw_ver.major,
-		&host->hw_ver.minor, &host->hw_ver.step);
 	ufs_qcom_advertise_quirks(hba);
 
 	hba->caps |= UFSHCD_CAP_CLK_GATING |
@@ -1277,21 +1294,6 @@ static int ufs_qcom_init(struct ufs_hba *hba)
 	hba->caps |= UFSHCD_CAP_HIBERN8_ENTER_ON_IDLE;
 	ufs_qcom_setup_clocks(hba, true);
 
-	/* "dev_ref_clk_ctrl_mem" is optional resource */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-	if (!res) {
-		dev_dbg(dev, "%s: dev_ref_clk_ctrl_mem resource not found\n",
-			__func__);
-	} else {
-		host->dev_ref_clk_ctrl_mmio = devm_ioremap_resource(dev, res);
-		if (IS_ERR(host->dev_ref_clk_ctrl_mmio)) {
-			dev_warn(dev,
-				"%s: could not map dev_ref_clk_ctrl_mmio, err %ld\n",
-				__func__, PTR_ERR(host->dev_ref_clk_ctrl_mmio));
-			host->dev_ref_clk_ctrl_mmio = NULL;
-		}
-	}
-
 	if (hba->dev->id < MAX_UFS_QCOM_HOSTS)
 		ufs_qcom_hosts[hba->dev->id] = host;