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authorBruce Allan <bruce.w.allan@intel.com>2009-10-22 21:22:18 -0700
committerDavid S. Miller <davem@davemloft.net>2009-10-22 21:22:18 -0700
commit74eee2e8d08048c847d1998c686e12a477ff939a (patch)
treea82f79cb2ee1ca213190db63aba066972d0063cf /drivers/sn
parent2bd9af046fdc10703b266b0f3b25423f0b7d703e (diff)
e1000e: reset the PHY on 82577/82578 when going to Sx
The PHY on 82577/82578 parts needs a soft reset when transitioning to Sx state in order for the PHY write which disables gigabit speed to take effect. Gigabit speed must be disabled in order for the PHY writes to registers on page 800 (the wakeup control registers) to work as expected otherwise the system might not wake via WoL. Signed-off-by: Bruce Allan <bruce.w.allan@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/sn')
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