diff options
| author | Prashanth Bhatta <bhattap@codeaurora.org> | 2016-10-13 23:21:48 -0700 |
|---|---|---|
| committer | Prashanth Bhatta <bhattap@codeaurora.org> | 2016-10-13 23:22:23 -0700 |
| commit | 312d5909bbb3aeac23c7c9f52725145b6a0a020d (patch) | |
| tree | 62e4619980b2416033de27fd25a4dcb0bb9bd654 /drivers/soc | |
| parent | fac2c0da16c3567c4838de4af0b794ecc55f1d0a (diff) | |
icnss: Switch to CXO before XO disable
During hardware reset if XO gets disabled and while polling to
confirm XO is disabled, bus timeout is noticed. So add
instructions to switch to CXO before disabling XO.
CRs-fixed: 1076441
Change-Id: Ia893786de4689e07f8d99d1ba3d8f1d6efcc7686
Signed-off-by: Prashanth Bhatta <bhattap@codeaurora.org>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/qcom/icnss.c | 53 |
1 files changed, 45 insertions, 8 deletions
diff --git a/drivers/soc/qcom/icnss.c b/drivers/soc/qcom/icnss.c index 2aa588ba610b..461de881adaa 100644 --- a/drivers/soc/qcom/icnss.c +++ b/drivers/soc/qcom/icnss.c @@ -108,6 +108,18 @@ module_param(qmi_timeout, ulong, 0600); #define WCSS_CLK_CTL_WCSS_CSS_GDSCR_HW_CONTROL BIT(1) #define WCSS_CLK_CTL_WCSS_CSS_GDSCR_PWR_ON BIT(31) +#define WCSS_CLK_CTL_NOC_CMD_RCGR_OFFSET 0x1D1030 +#define WCSS_CLK_CTL_NOC_CMD_RCGR_UPDATE BIT(0) + +#define WCSS_CLK_CTL_NOC_CFG_RCGR_OFFSET 0x1D1034 +#define WCSS_CLK_CTL_NOC_CFG_RCGR_SRC_SEL GENMASK(10, 8) + +#define WCSS_CLK_CTL_REF_CMD_RCGR_OFFSET 0x1D602C +#define WCSS_CLK_CTL_REF_CMD_RCGR_UPDATE BIT(0) + +#define WCSS_CLK_CTL_REF_CFG_RCGR_OFFSET 0x1D6030 +#define WCSS_CLK_CTL_REF_CFG_RCGR_SRC_SEL GENMASK(10, 8) + /* * Registers: WCSS_HM_A_WIFI_APB_3_A_WCMN_MAC_WCMN_REG * Base Address: 0x18AF0000 @@ -1087,7 +1099,7 @@ static void icnss_hw_io_reset(struct icnss_priv *priv, bool on) } } -int icnss_hw_reset_wlan_ss_power_down(struct icnss_priv *priv) +static int icnss_hw_reset_wlan_ss_power_down(struct icnss_priv *priv) { u32 rdata; @@ -1119,7 +1131,7 @@ int icnss_hw_reset_wlan_ss_power_down(struct icnss_priv *priv) return 0; } -int icnss_hw_reset_common_ss_power_down(struct icnss_priv *priv) +static int icnss_hw_reset_common_ss_power_down(struct icnss_priv *priv) { u32 rdata; @@ -1164,7 +1176,7 @@ int icnss_hw_reset_common_ss_power_down(struct icnss_priv *priv) } -int icnss_hw_reset_wlan_rfactrl_power_down(struct icnss_priv *priv) +static int icnss_hw_reset_wlan_rfactrl_power_down(struct icnss_priv *priv) { u32 rdata; @@ -1194,7 +1206,7 @@ int icnss_hw_reset_wlan_rfactrl_power_down(struct icnss_priv *priv) return 0; } -void icnss_hw_wsi_cmd_error_recovery(struct icnss_priv *priv) +static void icnss_hw_wsi_cmd_error_recovery(struct icnss_priv *priv) { icnss_pr_dbg("RESET: WSI CMD Error recovery, state: 0x%lx\n", priv->state); @@ -1218,7 +1230,7 @@ void icnss_hw_wsi_cmd_error_recovery(struct icnss_priv *priv) PMM_WSI_CMD_SW_BUS_SYNC, 0); } -u32 icnss_hw_rf_register_read_command(struct icnss_priv *priv, u32 addr) +static u32 icnss_hw_rf_register_read_command(struct icnss_priv *priv, u32 addr) { u32 rdata = 0; int ret; @@ -1267,7 +1279,7 @@ u32 icnss_hw_rf_register_read_command(struct icnss_priv *priv, u32 addr) return rdata; } -int icnss_hw_reset_rf_reset_cmd(struct icnss_priv *priv) +static int icnss_hw_reset_rf_reset_cmd(struct icnss_priv *priv) { u32 rdata; int ret; @@ -1321,7 +1333,30 @@ int icnss_hw_reset_rf_reset_cmd(struct icnss_priv *priv) return 0; } -int icnss_hw_reset_xo_disable_cmd(struct icnss_priv *priv) +static int icnss_hw_reset_switch_to_cxo(struct icnss_priv *priv) +{ + icnss_pr_dbg("RESET: Switch to CXO, state: 0x%lx\n", priv->state); + + icnss_hw_write_reg_field(priv->mem_base_va, + WCSS_CLK_CTL_NOC_CFG_RCGR_OFFSET, + WCSS_CLK_CTL_NOC_CFG_RCGR_SRC_SEL, 0); + + icnss_hw_write_reg_field(priv->mem_base_va, + WCSS_CLK_CTL_NOC_CMD_RCGR_OFFSET, + WCSS_CLK_CTL_NOC_CMD_RCGR_UPDATE, 1); + + icnss_hw_write_reg_field(priv->mem_base_va, + WCSS_CLK_CTL_REF_CFG_RCGR_OFFSET, + WCSS_CLK_CTL_REF_CFG_RCGR_SRC_SEL, 0); + + icnss_hw_write_reg_field(priv->mem_base_va, + WCSS_CLK_CTL_REF_CMD_RCGR_OFFSET, + WCSS_CLK_CTL_REF_CMD_RCGR_UPDATE, 1); + + return 0; +} + +static int icnss_hw_reset_xo_disable_cmd(struct icnss_priv *priv) { int ret; @@ -1369,7 +1404,7 @@ int icnss_hw_reset_xo_disable_cmd(struct icnss_priv *priv) return 0; } -int icnss_hw_reset(struct icnss_priv *priv) +static int icnss_hw_reset(struct icnss_priv *priv) { u32 rdata; u32 rdata1; @@ -1427,6 +1462,8 @@ int icnss_hw_reset(struct icnss_priv *priv) icnss_hw_reset_rf_reset_cmd(priv); + icnss_hw_reset_switch_to_cxo(priv); + icnss_hw_reset_xo_disable_cmd(priv); icnss_hw_write_reg_field(priv->mpm_config_va, MPM_WCSSAON_CONFIG_OFFSET, |