diff options
| author | Gaurav Kohli <gkohli@codeaurora.org> | 2016-10-22 14:53:24 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-10-25 02:00:36 -0700 |
| commit | 3ff1fcbead60eae925a8ea2755797886c862e882 (patch) | |
| tree | f075e07f69d8bddebde9a7dee20d05fbf3aab692 /drivers/soc | |
| parent | 46aa49c1188a77f52dc4969f82292c176d8f399b (diff) | |
soc: qcom: pil-q6v5: Add support for qdspv62.1.5 reset
Update the reset sequence to support qdspv62-1-5 for MSMFALCON.
Also Enable one more memory bank during reset sequence for MSMFALCON.
Change-Id: Ib0d27c13c0ebdfac629c1469c9a91a0b84d03640
Signed-off-by: Gaurav Kohli <gkohli@codeaurora.org>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/qcom/pil-q6v5.c | 16 | ||||
| -rw-r--r-- | drivers/soc/qcom/pil-q6v5.h | 1 |
2 files changed, 14 insertions, 3 deletions
diff --git a/drivers/soc/qcom/pil-q6v5.c b/drivers/soc/qcom/pil-q6v5.c index f8895e8a7b3d..5752aecb82bd 100644 --- a/drivers/soc/qcom/pil-q6v5.c +++ b/drivers/soc/qcom/pil-q6v5.c @@ -388,7 +388,7 @@ static int __pil_q6v55_reset(struct pil_desc *pil) mb(); udelay(1); - if (drv->qdsp6v62_1_2) { + if (drv->qdsp6v62_1_2 || drv->qdsp6v62_1_5) { for (i = BHS_CHECK_MAX_LOOPS; i > 0; i--) { if (readl_relaxed(drv->reg_base + QDSP6V62SS_BHS_STATUS) & QDSP6v55_BHS_EN_REST_ACK) @@ -488,7 +488,8 @@ static int __pil_q6v55_reset(struct pil_desc *pil) */ udelay(1); } - } else if (drv->qdsp6v61_1_1 || drv->qdsp6v62_1_2) { + } else if (drv->qdsp6v61_1_1 || drv->qdsp6v62_1_2 || + drv->qdsp6v62_1_5) { /* Deassert QDSP6 compiler memory clamp */ val = readl_relaxed(drv->reg_base + QDSP6SS_PWR_CTL); val &= ~QDSP6v55_CLAMP_QMC_MEM; @@ -501,7 +502,13 @@ static int __pil_q6v55_reset(struct pil_desc *pil) /* Turn on L1, L2, ETB and JU memories 1 at a time */ val = readl_relaxed(drv->reg_base + QDSP6V6SS_MEM_PWR_CTL); - for (i = 28; i >= 0; i--) { + + if (drv->qdsp6v62_1_5) + i = 29; + else + i = 28; + + for ( ; i >= 0; i--) { val |= BIT(i); writel_relaxed(val, drv->reg_base + QDSP6V6SS_MEM_PWR_CTL); @@ -663,6 +670,9 @@ struct q6v5_data *pil_q6v5_init(struct platform_device *pdev) drv->qdsp6v62_1_2 = of_property_read_bool(pdev->dev.of_node, "qcom,qdsp6v62-1-2"); + drv->qdsp6v62_1_5 = of_property_read_bool(pdev->dev.of_node, + "qcom,qdsp6v62-1-5"); + drv->non_elf_image = of_property_read_bool(pdev->dev.of_node, "qcom,mba-image-is-not-elf"); diff --git a/drivers/soc/qcom/pil-q6v5.h b/drivers/soc/qcom/pil-q6v5.h index 6a59b06f7b6c..9e8b8511e69b 100644 --- a/drivers/soc/qcom/pil-q6v5.h +++ b/drivers/soc/qcom/pil-q6v5.h @@ -62,6 +62,7 @@ struct q6v5_data { bool qdsp6v56_1_10; bool qdsp6v61_1_1; bool qdsp6v62_1_2; + bool qdsp6v62_1_5; bool non_elf_image; bool restart_reg_sec; bool override_acc; |