diff options
| author | Alok Chauhan <alokc@codeaurora.org> | 2018-01-26 02:19:18 +0530 |
|---|---|---|
| committer | Alok Chauhan <alokc@codeaurora.org> | 2018-01-31 11:54:13 +0530 |
| commit | 363bbeba93346dd8551467d4bc26a9643ed9526c (patch) | |
| tree | 0ee9273f80a33de478c5b6815fdd54f1f6286bef /drivers/spi | |
| parent | 4938bb02a80abb5de1f6e9e3d43c0ff16b4a99de (diff) | |
spi: spi_qsd: Correct SPI slave hw init sequence
While configuring QUP in SPI slave mode, an internal
HW signal needs to propagate from AHB clock domain
to SPI core clock domain. To make sure a safe and
correct propagation of this signal the software should
perform the SPI HW init sequence in proper order.
Change-Id: Ied621bb5d1ba793ce48c5a6a0f6be3b86b3a6773
Signed-off-by: Alok Chauhan <alokc@codeaurora.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi_qsd.c | 27 |
1 files changed, 23 insertions, 4 deletions
diff --git a/drivers/spi/spi_qsd.c b/drivers/spi/spi_qsd.c index 5fd1565d692f..aa7386325893 100644 --- a/drivers/spi/spi_qsd.c +++ b/drivers/spi/spi_qsd.c @@ -1799,10 +1799,7 @@ static void msm_spi_slv_setup(struct msm_spi *dd) u32 irq_en = GENMASK(6, 0); qup_config &= ~QUP_CFG_MODE; - qup_config |= QUP_CONFIG_SPI_SLAVE; - qup_config |= (SPI_EN_EXT_OUT_FLAG | APP_CLK_ON_EN | CORE_CLK_ON_EN - | FIFO_CLK_ON_EN | CORE_EX_CLK_ON_EN); - spi_config |= SPI_CFG_SLAVE_OP; + qup_config |= SPI_EN_EXT_OUT_FLAG; writel_relaxed(qup_config, dd->base + QUP_CONFIG); writel_relaxed(spi_config, dd->base + SPI_CONFIG); writel_relaxed(irq_en, (dd->base + SPI_SLAVE_IRQ_EN)); @@ -1813,6 +1810,28 @@ static void msm_spi_slv_setup(struct msm_spi *dd) writel_relaxed(slv_cfg, (dd->base + SPI_SLAVE_CONFIG)); } /* + * Ensure the previous write completed before enabling slave mode. + */ + mb(); + + spi_config = readl_relaxed(dd->base + SPI_CONFIG); + qup_config = readl_relaxed(dd->base + QUP_CONFIG); + + qup_config |= QUP_CONFIG_SPI_SLAVE; + spi_config |= SPI_CFG_SLAVE_OP; + + writel_relaxed(qup_config, dd->base + QUP_CONFIG); + writel_relaxed(spi_config, dd->base + SPI_CONFIG); + /* + * Ensure the previous write completed before enabling clk_on bit. + */ + mb(); + + qup_config = readl_relaxed(dd->base + QUP_CONFIG); + qup_config |= (APP_CLK_ON_EN | CORE_CLK_ON_EN | + FIFO_CLK_ON_EN | CORE_EX_CLK_ON_EN); + writel_relaxed(qup_config, dd->base + QUP_CONFIG); + /* * Ensure Slave setup completes before returning. */ mb(); |