diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2009-11-02 14:26:38 +0000 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-11-02 23:39:05 -0800 |
| commit | 0e5f784c77197edf29d2770b518dc78777d5a480 (patch) | |
| tree | 92b4e99661a56fe9ea324feb39cccda5c01c3bf6 /drivers | |
| parent | 788a035e6061a66c6c77059c417fdc6234e140ff (diff) | |
tg3: Add AC131 power down support
The AC131 does not respect the power down bit (bit 11) of the MII
Control Register (reg 0x0). Instead, software is required to put the
phy into standby power down mode through the shadow register set. This
patch implements support for the AC131 standby power down mode.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/tg3.c | 20 | ||||
| -rw-r--r-- | drivers/net/tg3.h | 3 |
2 files changed, 23 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index a43ef2b3a530..003ab53cf613 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c @@ -2149,6 +2149,26 @@ static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ); udelay(40); return; + } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) { + u32 phytest; + if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { + u32 phy; + + tg3_writephy(tp, MII_ADVERTISE, 0); + tg3_writephy(tp, MII_BMCR, + BMCR_ANENABLE | BMCR_ANRESTART); + + tg3_writephy(tp, MII_TG3_FET_TEST, + phytest | MII_TG3_FET_SHADOW_EN); + if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { + phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD; + tg3_writephy(tp, + MII_TG3_FET_SHDW_AUXMODE4, + phy); + } + tg3_writephy(tp, MII_TG3_FET_TEST, phytest); + } + return; } else if (do_low_power) { tg3_writephy(tp, MII_TG3_EXT_CTRL, MII_TG3_EXT_CTRL_FORCE_LED_OFF); diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 68431da5aad3..9999345a11a4 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h @@ -2080,6 +2080,9 @@ #define MII_TG3_FET_SHDW_MISCCTRL 0x10 #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000 +#define MII_TG3_FET_SHDW_AUXMODE4 0x1a +#define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008 + #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020 |