diff options
author | Venkat Gopalakrishnan <venkatg@codeaurora.org> | 2015-01-09 12:19:16 -0800 |
---|---|---|
committer | Subhash Jadavani <subhashj@codeaurora.org> | 2016-05-31 15:26:07 -0700 |
commit | 3ef53ed8d2dd08999120f97c77ba0f8e2ec40047 (patch) | |
tree | 4225106f71c61c564e25f80637887438b4ea97af /drivers | |
parent | e71e9559d4327b8b48035bcf6947d646b44e46b8 (diff) |
mmc: sdhci-msm: Update mmc DDR timing mode
A new timing mode has been introduced to differentiate SD/MMC
DDR timing modes. Use the MMC specific DDR timing mode in addition
to the SD specific one when checking for timing modes.
Change-Id: Id151c0fd0dc8eccdec8f842a5ee13af415b7ffe6
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mmc/host/sdhci-msm.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 3f242fa5307d..b3237a710b3c 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2521,6 +2521,7 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock) sup_clock = sdhci_msm_get_sup_clk_rate(host, clock); if ((curr_ios.timing == MMC_TIMING_UHS_DDR50) || + (curr_ios.timing == MMC_TIMING_MMC_DDR52) || (curr_ios.timing == MMC_TIMING_MMC_HS400)) { /* * The SDHC requires internal clock frequency to be double the @@ -2645,9 +2646,9 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); /* Select Bus Speed Mode for host */ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; - if (uhs == MMC_TIMING_MMC_HS400) - ctrl_2 |= SDHCI_CTRL_UHS_SDR104; - else if (uhs == MMC_TIMING_MMC_HS200) + if ((uhs == MMC_TIMING_MMC_HS400) || + (uhs == MMC_TIMING_MMC_HS200) || + (uhs == MMC_TIMING_UHS_SDR104)) ctrl_2 |= SDHCI_CTRL_UHS_SDR104; else if (uhs == MMC_TIMING_UHS_SDR12) ctrl_2 |= SDHCI_CTRL_UHS_SDR12; @@ -2655,9 +2656,8 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, ctrl_2 |= SDHCI_CTRL_UHS_SDR25; else if (uhs == MMC_TIMING_UHS_SDR50) ctrl_2 |= SDHCI_CTRL_UHS_SDR50; - else if (uhs == MMC_TIMING_UHS_SDR104) - ctrl_2 |= SDHCI_CTRL_UHS_SDR104; - else if (uhs == MMC_TIMING_UHS_DDR50) + else if ((uhs == MMC_TIMING_UHS_DDR50) || + (uhs == MMC_TIMING_MMC_DDR52)) ctrl_2 |= SDHCI_CTRL_UHS_DDR50; /* * When clock frquency is less than 100MHz, the feedback clock must be |