drm/msm: Correctly retrieve gpu's active power level

The parsing logic wrongly assumes the position of the initial/active power
level value in the gpu dts file. This leads to the active power level
always defaulting to a value of 1. Look for the initial power level
one level up in the device tree.

Change-Id: I63f8c8efd05ad3693c6f399f58bed44ac84105d2
Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>

1 files changed, 9 insertions, 8 deletions

diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
index d397c44f1203..e8cc0257b943 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
@@ -394,14 +394,6 @@ static int _adreno_get_pwrlevels(struct msm_gpu *gpu, struct device_node *node)
 {
 	struct device_node *child;
 
-	gpu->active_level = 1;
-
-	/* The device tree will tell us the best clock to initialize with */
-	of_property_read_u32(node, "qcom,initial-pwrlevel", &gpu->active_level);
-
-	if (gpu->active_level >= ARRAY_SIZE(gpu->gpufreq))
-		gpu->active_level = 1;
-
 	for_each_child_of_node(node, child) {
 		unsigned int index;
 
@@ -450,6 +442,15 @@ static int adreno_get_pwrlevels(struct msm_gpu *gpu, struct device_node *parent)
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 	struct device_node *node, *child;
 
+	gpu->active_level = 1;
+
+	/* The device tree will tell us the best clock to initialize with */
+	of_property_read_u32(parent, "qcom,initial-pwrlevel",
+			&gpu->active_level);
+
+	if (gpu->active_level >= ARRAY_SIZE(gpu->gpufreq))
+		gpu->active_level = 1;
+
 	/* See if the target has defined a number of power bins */
 	node = of_find_node_by_name(parent, "qcom,gpu-pwrlevel-bins");
 	if (!node) {