diff options
| author | Tony Truong <truong@codeaurora.org> | 2015-01-28 17:08:04 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:09:03 -0700 |
| commit | b0ac5910b0590417758ad326389ce183b0c5207a (patch) | |
| tree | db8ca75d4c755fc11411ac09f187490f401922de /drivers | |
| parent | b80470b0c1be9c496af542a98eec0ae31d2cc5c3 (diff) | |
msm: pcie: add support to enable common clk config for EP
Add support to enable the common clock configuration for the
endpoint.
Change-Id: I9f6c33eb6cfa032837a07e437f349a7c1a60704c
Signed-off-by: Tony Truong <truong@codeaurora.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pci/host/pci-msm.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 0ca874fbc763..7f3ab113bfbd 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -493,6 +493,7 @@ struct msm_pcie_dev_t { bool l0s_supported; bool l1_supported; bool l1ss_supported; + bool common_clk_en; bool aux_clk_sync; uint32_t n_fts; bool ext_ref_clk; @@ -1101,6 +1102,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) dev->l1_supported ? "" : "not"); pr_alert("l1ss_supported is %s supported\n", dev->l1ss_supported ? "" : "not"); + pr_alert("common_clk_en is %d\n", + dev->common_clk_en); pr_alert("aux_clk_sync is %d\n", dev->aux_clk_sync); pr_alert("ext_ref_clk is %d\n", @@ -2653,6 +2656,19 @@ static void msm_pcie_config_link_state(struct msm_pcie_dev_t *dev) dev->rc_idx, ep_link_cap_offset); } + if (dev->common_clk_en) { + msm_pcie_write_mask(dev->conf + ep_link_ctrlstts_offset, + 0, BIT(6)); + + if (dev->shadow_en) + dev->ep_shadow[0][ep_link_ctrlstts_offset / 4] = + readl_relaxed(dev->conf + + ep_link_ctrlstts_offset); + + PCIE_DBG2(dev, "EP's CAP_LINKCTRLSTATUS:0x%x\n", + readl_relaxed(dev->conf + ep_link_ctrlstts_offset)); + } + if (dev->l0s_supported) { msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS, 0, BIT(0)); @@ -4351,6 +4367,14 @@ static int msm_pcie_probe(struct platform_device *pdev) "qcom,l1ss-supported"); PCIE_DBG(&msm_pcie_dev[rc_idx], "L1ss is %s supported.\n", msm_pcie_dev[rc_idx].l1ss_supported ? "" : "not"); + msm_pcie_dev[rc_idx].common_clk_en = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,common-clk-en"); + PCIE_DBG(&msm_pcie_dev[rc_idx], "Common clock is %s enabled.\n", + msm_pcie_dev[rc_idx].common_clk_en ? "" : "not"); + msm_pcie_dev[rc_idx].aux_clk_sync = + of_property_read_bool((&pdev->dev)->of_node, + "qcom,aux-clk-sync"); msm_pcie_dev[rc_idx].aux_clk_sync = of_property_read_bool((&pdev->dev)->of_node, "qcom,aux-clk-sync"); |