diff options
| author | Yan He <yanhe@codeaurora.org> | 2015-05-29 14:42:52 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:16:09 -0700 |
| commit | d7de1f12d856e6e7c853a7f69204cba5d7b74ee5 (patch) | |
| tree | cd9bd98ff5e20184b8ffdde8687ce534f6ee45ea /drivers | |
| parent | f31be11ecb7d33f4dccfbcc358ca059b214b3c5c (diff) | |
msm: ep_pcie: add L1ss support
Enable L1ss support in L1ss capability register.
Change-Id: I51e6e1bbd8073e7bb88c7e041199d862db020ae7
Signed-off-by: Yan He <yanhe@codeaurora.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/platform/msm/ep_pcie/ep_pcie_core.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 0b8517e5b8b7..d6f32fac2fb6 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -536,8 +536,8 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev) ep_pcie_write_reg_field(dev->dm_core, PCIE20_LINK_CAPABILITIES, PCIE20_MASK_L0S_EXIT_LATENCY, 0x6); - /* L1ss is not supported */ - ep_pcie_write_mask(dev->dm_core + PCIE20_L1SUB_CAPABILITY, 0x1f, 0); + /* L1ss is supported */ + ep_pcie_write_mask(dev->dm_core + PCIE20_L1SUB_CAPABILITY, 0, 0x1f); /* Enable Clock Power Management */ ep_pcie_write_reg_field(dev->dm_core, PCIE20_LINK_CAPABILITIES, |