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authorMatthew Wilcox <matthew@wil.cx>2006-10-10 08:01:21 -0600
committerGreg Kroah-Hartman <gregkh@suse.de>2006-12-01 14:36:57 -0800
commitedb2d97eb57b7a21c9256260562de6a65dda86cc (patch)
treec07b98d0e14256e6a91709c39e55074d5ffcc05e /drivers
parentebf5a24829def5d066922ceebde61dd57fdc6b1e (diff)
PCI: Replace HAVE_ARCH_PCI_MWI with PCI_DISABLE_MWI
pSeries is the only architecture left using HAVE_ARCH_PCI_MWI and it's really inappropriate for its needs. It really wants to disable MWI altogether. So here are a pair of stub implementations for pci_set_mwi and pci_clear_mwi. Also rename pci_generic_prep_mwi to pci_set_cacheline_size since that better reflects what it does. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Cc: Paul Mackerras <paulus@samba.org> Acked-by: Jeff Garzik <jeff@garzik.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/pci/pci.c31
1 files changed, 18 insertions, 13 deletions
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index bc88c30a418b..427991741cf3 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -875,7 +875,17 @@ pci_set_master(struct pci_dev *dev)
pcibios_set_master(dev);
}
-#ifndef HAVE_ARCH_PCI_MWI
+#ifdef PCI_DISABLE_MWI
+int pci_set_mwi(struct pci_dev *dev)
+{
+ return 0;
+}
+
+void pci_clear_mwi(struct pci_dev *dev)
+{
+}
+
+#else
#ifndef PCI_CACHE_LINE_BYTES
#define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
@@ -886,17 +896,17 @@ pci_set_master(struct pci_dev *dev)
u8 pci_cache_line_size = PCI_CACHE_LINE_BYTES / 4;
/**
- * pci_generic_prep_mwi - helper function for pci_set_mwi
- * @dev: the PCI device for which MWI is enabled
+ * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
+ * @dev: the PCI device for which MWI is to be enabled
*
- * Helper function for generic implementation of pcibios_prep_mwi
- * function. Originally copied from drivers/net/acenic.c.
+ * Helper function for pci_set_mwi.
+ * Originally copied from drivers/net/acenic.c.
* Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
*
* RETURNS: An appropriate -ERRNO error value on error, or zero for success.
*/
static int
-pci_generic_prep_mwi(struct pci_dev *dev)
+pci_set_cacheline_size(struct pci_dev *dev)
{
u8 cacheline_size;
@@ -922,7 +932,6 @@ pci_generic_prep_mwi(struct pci_dev *dev)
return -EINVAL;
}
-#endif /* !HAVE_ARCH_PCI_MWI */
/**
* pci_set_mwi - enables memory-write-invalidate PCI transaction
@@ -940,12 +949,7 @@ pci_set_mwi(struct pci_dev *dev)
int rc;
u16 cmd;
-#ifdef HAVE_ARCH_PCI_MWI
- rc = pcibios_prep_mwi(dev);
-#else
- rc = pci_generic_prep_mwi(dev);
-#endif
-
+ rc = pci_set_cacheline_size(dev);
if (rc)
return rc;
@@ -976,6 +980,7 @@ pci_clear_mwi(struct pci_dev *dev)
pci_write_config_word(dev, PCI_COMMAND, cmd);
}
}
+#endif /* ! PCI_DISABLE_MWI */
/**
* pci_intx - enables/disables PCI INTx for device dev